MAX® 10 FPGA Developer Center

The FPGA Developer Center is organized into industry-standard stages, which provides you with various resources to complete your FPGA design. Each design step is detailed in the expandable sub-sections with links that allow you to select and move between the various Generation 10 device series.

1. Device Information

Documentation

User Guides / Device Overview / Device Datasheet / Application Notes
MAX® 10 FPGA Device Datasheet
MAX® 10 Clocking and PLL User Guide
MAX® 10 Analog to Digital Converter User Guide
MAX® 10 FPGA Device Overview
MAX® 10 General Purpose I/O User Guide
MAX® 10 High-Speed LVDS I/O User Guide
MAX® 10 FPGA Configuration User Guide
MAX® 10 Power Management User Guide
MAX® 10 Embedded Memory User Guide
MAX® 10 FPGA Device Architecture
MAX® 10 User Flash Memory User Guide
MAX® 10 FPGA Signal Integrity Design Guidelines
MAX® 10 FPGA Device Family Pin Connection Guidelines
MAX® 10 FPGA Design Guidelines
FPGA Parallel Flash Loader IP Core User Guide
FPGAs Remote Update IP Core User Guide
AN 286: Implementing LED Drivers in Altera MAX® Series
AN 773: Drive-On-Chip Reference Design for MAX® 10 Devices
AN 100: In-System Programmability Guidelines
AN 265: Using Altera MAX® Series as Microcontroller I/O Expanders
AN 294: Crosspoint Switch Matrices in Altera MAX® Series
AN 425: Using the Command-Line Jam STAPL Solution for Device Programming
AN 447: Interfacing FPGA Devices with 3.3/3.0/2.5 V LVTTL/LVCMOS I/O Systems
AN 486: SPI to I2C Using Altera MAX® Series
AN 488: Stepper Motor Controller Using Altera MAX® Series
AN 490: Altera MAX® Series as Voltage Level Shifters
AN 491: Power Sequence Auto Start Using Altera MAX® Series
AN 492: CF+ Interface Using Altera MAX® Series
AN 493: I2C Battery Gauge Interface Using Altera MAX® Series
AN 494: GPIO Pin Expansion Using I2C Bus Interface in Altera MAX® Series
AN 495: IDE/ATA Controller Using Altera MAX® Series
AN 496: Using the Internal Oscillator IP Core
AN 498: LED Blink Using Power Sequencing in Altera MAX® Series
AN 500: NAND Flash Memory Interface with Altera MAX® Series
AN 501: Pulse Width Modulation Using Altera MAX® Series
AN 502: Implementing SMBus Controller in Altera MAX® Series
AN 509: Multiplexing SDIO Devices Using Altera MAX® Series
AN 522: Implementing Bus LVDS Interface in Supported FPGA Device Families
AN 630: Real-Time ISP and ISP Clamp for FPGAs MAX® Series
AN 631: Replacing Serial EEPROMs with User Flash Memory in FPGAs MAX® Series
AN 741: Remote System Upgrade for MAX® 10 FPGA Devices over UART with the Nios® II Processor
AN 752: Guidelines for Handling Altera Wafer Level Chip Scale Package (WLCSP)
AN 370: Using the FPGA Serial Flash Loader with the Quartus® Prime Software

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MAX® 10 FPGA Developer Center

1. Device Information

2. Interface Protocols

3. Design Planning

4. Design Entry

5. Simulation and Verification

6. Implementation and Optimization

7. Timing Analysis

8. On-Chip Debug

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