Intel® MAX® 10 FPGA Signal Integrity Design Guidelines

ID 683572
Date 10/31/2022

Intel® MAX® 10 FPGA Signal Integrity Design Guidelines

Today’s complex FPGA system design is incomplete without addressing the integrity of signals coming in to and out of the FPGA. Simultaneous switching noise (SSN) often leads to the degradation of signal integrity by causing signal distortion, thereby reducing the noise margin of a system.

To avoid signal integrity issues, Intel recommends that you follow the design considerations, I/O placement guidelines, and board design guidelines for Intel® MAX® 10 devices regarding:

  • I/O placement rules
  • Voltage-referenced I/O standards
  • High-speed LVDS, phase-locked loops (PLLs), and clocking
  • External memory interfaces
  • Analog to digital converter

Intel recommends that you perform SSN analysis early in your FPGA design, before the layout of your PCB.

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