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1.1. Definitions
1.2. Understanding SSN
1.3. Guidelines: Data Input Pin
1.4. Guidelines: Clock and Asynchronous Control Input Signal
1.5. Guidelines: Clock and Data Input Signal for MAX® 10 E144 Package
1.6. Guidelines: I/O Restriction Rules
1.7. Guidelines: Placement Restrictions for 1.0 V I/O Pin
1.8. Guidelines: LVTTL/LVCMOS I/O Utilization for MAX® 10 FPGA Package B610
1.9. Guidelines: External Memory Interface I/O Restrictions
1.10. Guidelines: Board Design Requirement for DDR2, DDR3, and LPDDR2
1.11. Guidelines: Analog-to-Digital Converter I/O Restriction
1.12. Guidelines: Voltage-Referenced I/O Standards Restriction
1.13. Guidelines: Adhere to the LVDS I/O Restrictions Rules
1.14. Guidelines: Enable Clamp Diode for LVTTL/LVCMOS Input Buffers
1.15. Guidelines: ADC Ground Plane Connection
1.16. Guidelines: Board Design for ADC Reference Voltage Pin
1.17. Guidelines: Board Design for Analog Input
1.18. Guidelines: Board Design for Power Supply Pin and ADC Ground (REFGND)
1.19. Guidelines: MAX® 10 Variable Pitch BGA (VPBGA) Package Overview and Board Fan-Out Recommendations
1.20. Document Revision History for the MAX® 10 FPGA Signal Integrity Design Guidelines
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1. MAX® 10 FPGA Signal Integrity Design Guidelines
Today’s complex FPGA system design is incomplete without addressing the integrity of signals coming in to and out of the FPGA. Simultaneous switching noise (SSN) often leads to the degradation of signal integrity by causing signal distortion, thereby reducing the noise margin of a system.
To avoid signal integrity issues, Altera recommends that you follow the design considerations, I/O placement guidelines, and board design guidelines for MAX® 10 devices regarding:
- I/O placement rules
- Voltage-referenced I/O standards
- High-speed LVDS, phase-locked loops (PLLs), and clocking
- External memory interfaces
- Analog to digital converter
Altera recommends that you perform SSN analysis early in your FPGA design, before the layout of your PCB.
Section Content
Definitions
Understanding SSN
Guidelines: Data Input Pin
Guidelines: Clock and Asynchronous Control Input Signal
Guidelines: Clock and Data Input Signal for MAX 10 E144 Package
Guidelines: I/O Restriction Rules
Guidelines: Placement Restrictions for 1.0 V I/O Pin
Guidelines: LVTTL/LVCMOS I/O Utilization for MAX 10 FPGA Package B610
Guidelines: External Memory Interface I/O Restrictions
Guidelines: Board Design Requirement for DDR2, DDR3, and LPDDR2
Guidelines: Analog-to-Digital Converter I/O Restriction
Guidelines: Voltage-Referenced I/O Standards Restriction
Guidelines: Adhere to the LVDS I/O Restrictions Rules
Guidelines: Enable Clamp Diode for LVTTL/LVCMOS Input Buffers
Guidelines: ADC Ground Plane Connection
Guidelines: Board Design for ADC Reference Voltage Pin
Guidelines: Board Design for Analog Input
Guidelines: Board Design for Power Supply Pin and ADC Ground (REFGND)
Guidelines: MAX 10 Variable Pitch BGA (VPBGA) Package Overview and Board Fan-Out Recommendations
Document Revision History for the MAX 10 FPGA Signal Integrity Design Guidelines