Intel® MAX® 10 FPGA Signal Integrity Design Guidelines

ID 683572
Date 10/31/2022
Public

Guidelines: Enable Clamp Diode for LVTTL/LVCMOS Input Buffers

If the input voltage to the LVTTL/LVCMOS input buffers is higher than the VCCIO of the I/O bank, Intel recommends that you enable the clamp diode.
  • 3.3 V LVCMOS/LVTTL input buffers—enable clamp diode if VCCIO of the I/O bank is 3.0 V.
  • 3.3 V or 3.0 V LVCMOS/LVTTL input buffers—enable clamp diode if VCCIO of the I/O bank is 2.5 V.

By enabling the clamp diode under these conditions, you limit overshoot. However, this does not comply with hot socket current specification.

If you do not enable the clamp diode under these conditions, the signal integrity for the I/O pin is impacted and overshoot occurs. In this situation, you must ensure that your board design conforms to the overshoot specifications.

Table 10.  Voltage Tolerance Maximum Ratings for 3.3 V or 3.0 VThis table lists the voltage tolerance specifications. Ensure that your board design conforms to these specifications if you do not want to follow the clamp diode recommendation.
Voltage Minimum (V) Maximum (V)
VCCIO = 3.3 V 3.135 3.45
VCCIO = 3.0 V 2.85 3.15
VIH (AC) 4.1
VIH (DC) 3.6
VIL (DC) –0.3 0.8