MAX® 10 FPGA Signal Integrity Design Guidelines

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Date 3/17/2025
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Document Table of Contents
Document Table of Contents x
1. MAX® 10 FPGA Signal Integrity Design Guidelines
1. MAX® 10 FPGA Signal Integrity Design Guidelines x
1.1. Definitions 1.2. Understanding SSN 1.3. Guidelines: Data Input Pin 1.4. Guidelines: Clock and Asynchronous Control Input Signal 1.5. Guidelines: Clock and Data Input Signal for MAX® 10 E144 Package 1.6. Guidelines: I/O Restriction Rules 1.7. Guidelines: Placement Restrictions for 1.0 V I/O Pin 1.8. Guidelines: LVTTL/LVCMOS I/O Utilization for MAX® 10 FPGA Package B610 1.9. Guidelines: External Memory Interface I/O Restrictions 1.10. Guidelines: Board Design Requirement for DDR2, DDR3, and LPDDR2 1.11. Guidelines: Analog-to-Digital Converter I/O Restriction 1.12. Guidelines: Voltage-Referenced I/O Standards Restriction 1.13. Guidelines: Adhere to the LVDS I/O Restrictions Rules 1.14. Guidelines: Enable Clamp Diode for LVTTL/LVCMOS Input Buffers 1.15. Guidelines: ADC Ground Plane Connection 1.16. Guidelines: Board Design for ADC Reference Voltage Pin 1.17. Guidelines: Board Design for Analog Input 1.18. Guidelines: Board Design for Power Supply Pin and ADC Ground (REFGND) 1.19. Guidelines: MAX® 10 Variable Pitch BGA (VPBGA) Package Overview and Board Fan-Out Recommendations 1.20. Document Revision History for the MAX® 10 FPGA Signal Integrity Design Guidelines
1.4. Guidelines: Clock and Asynchronous Control Input Signal x
1.4.1. Schmitt-Trigger Input Buffer
1.7. Guidelines: Placement Restrictions for 1.0 V I/O Pin x
1.7.1. Calculating the Total Inductance for 1.0 V Pin Placement
1.8. Guidelines: LVTTL/LVCMOS I/O Utilization for MAX® 10 FPGA Package B610 x
1.8.1. GPIO SSO Estimator Tool for MAX® 10 FPGA Package B610
1.8.1. GPIO SSO Estimator Tool for MAX® 10 FPGA Package B610 x
1.8.1.1. GPIO SSO Estimator Tool for MAX® 10 FPGA Package B610 Parameters 1.8.1.2. GPIO SSO Estimator Tool for MAX® 10 FPGA Package B610 Result Analysis 1.8.1.3. GPIO SSO Estimator Tool for MAX® 10 FPGA Package B610 Result Mitigation
1.19. Guidelines: MAX® 10 Variable Pitch BGA (VPBGA) Package Overview and Board Fan-Out Recommendations x
1.19.1. Overview of MAX® 10 VPBGA 1.19.2. MAX® 10 VPBGA Board Fan-Out
1. MAX® 10 FPGA Signal Integrity Design Guidelines

1.19.2. MAX® 10 VPBGA Board Fan-Out

This section provides general recommendations on how to fan-out the MAX® 10 variable pitch BGA (VPBGA) devices.

For the VPBGA packaging board design, you must first understand the different ball pitches for different I/O functions at different locations in the package. Then, follow the guidance to plan the signal routing accordingly. If your board design is not sensitive to electromagnetic interference (EMI) and impedance tolerance, Altera recommends routing the four outer rings on the top layer to avoid the vias and simplify routing in the inner layer, as shown in Top Layer Fan-out Example figure.

The following figure shows an overview of a MAX® 10 B610 package. In the BGA center area, highlighted by the red box, the VPBGA adopts a 0.8 mm × 0.8 mm ball pitch, while the outer ring area uses a 0.5 mm × 0.94 mm ball pitch. Note that the 0.5 mm ball pitch is not meant for signal trace to route through. Refer to the fan out example in the Top Layer Fan-out Example and Inner Layer Fan-out Example figures for more details.

Figure 12. Overview of MAX® 10 B610 Package

Altera recommends the dog-bone fan-out structure for the MAX® 10 VPBGA devices. You can use a Type-III board stack-up for cost reduction.

Figure 13. Dog-bone Fan-out Structure

In the following routing example figure, vias with a 10-mil drill hole size and a 18-mil pad size are considered.

The outer layer adopts a 3.5 mil trace width and a 3.5 mil spacing (minimum 4 mils pad-to-trace) to fan out three traces from each routing channel. 4 mils/4 mils (line width/spacing) is adopted, and each routing channel can only accommodate two traces for fan-out.

Fabrication capabilities may vary between PCB manufacturers, but the demonstrated fan-out strategy in this example is common for the MAX® 10 VPBGA devices. Altera recommends using microstrip routing for GPIO pins located in the outer rows or columns on the top layer to avoid PTH vias, reduce the layer count, and simplify the inner layer routing. The 0.94 mm pitch at the outer ring area is sufficient to fan out two or three signal-ended traces on the outer layers, depending on the specific stack-up design.

Figure 14. Top Layer Fan-out Example

The following figure shows an example inner layer fan-out. Both single ended and differential structure can be adopted.

Figure 15. Inner Layer Fan-out Example

Fan-out more signals on each layer to help to reduce the total layer count. For EMIF signals, refer to the Guidelines: External Memory Interface I/O Restrictions section for more routing requirements such as skew, maximum trace length, and others.

For power pins, you can find relevant specifications for each power rail in the MAX® 10 FPGA Device Family Pin Connection Guidelines . Altera recommends following the requirements in the power distribution network design guidelines. For a lower inductance connection, it is advisable for the power vias to have a solid and unbroken connection to the power planes.

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