Intel® MAX® 10 FPGA Signal Integrity Design Guidelines

ID 683572
Date 10/31/2022

Guidelines: Clock and Asynchronous Control Input Signal

Input clock signal and asynchronous signals are sensitive signals. If signal interference happens at the signal edge, it can cause double sampling issue in internal logic.

PLLs are sensitive to SSN jitter generated by nearby I/O pins. Intel recommends that you do not use unterminated I/O standards in the same bank as the input clock signal to the PLL. Intel also recommends instantiating the input clock signal with full rail voltage.

Because edge noise is closer to the noise threshold (gap between maximum VIL and minimum VIH), the tolerable noise margin is smaller than the data signal. If the noise falls within the threshold range, sampling failure occurs.
Figure 6. Noise for Slow and Fast Clock Edges

Slower clock edges are more susceptible to jitter because the threshold range is wider than fast clock edges. Additionally, very slow clock edges are exposed to a larger amount of switching noise from the board to the device.

Follow these recommendations to avoid signal integrity issues:
  • Design with faster input clock edges.
  • Set the unused pin to a programmable ground pin to help in shielding the signal interference.
  • Terminate all unused pin. Unterminated unused pins can cause signal interference between the input clock pin and the unused pins when there is signal toggling. You can set the unused pin to:
    • Weak pull-up resistor to create high impedance termination; or
    • Programmable ground to help in shielding signal interference.
  • Reduce the slew rate or current strength of the adjacent strong aggressor pin.
  • Turn on the Schmitt trigger on the input buffer.
  • Avoid using dedicated LVDS signal as single-ended input clock signal. The strong mutual coupling originally targeted for LVDS signals can create distortion on single–ended input clock signal coming from another LVDS terminal.