MAX® 10 FPGA Signal Integrity Design Guidelines

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ID 683572
Date 3/17/2025
Public
Document Table of Contents
Document Table of Contents x
1. MAX® 10 FPGA Signal Integrity Design Guidelines
1. MAX® 10 FPGA Signal Integrity Design Guidelines x
1.1. Definitions 1.2. Understanding SSN 1.3. Guidelines: Data Input Pin 1.4. Guidelines: Clock and Asynchronous Control Input Signal 1.5. Guidelines: Clock and Data Input Signal for MAX® 10 E144 Package 1.6. Guidelines: I/O Restriction Rules 1.7. Guidelines: Placement Restrictions for 1.0 V I/O Pin 1.8. Guidelines: LVTTL/LVCMOS I/O Utilization for MAX® 10 FPGA Package B610 1.9. Guidelines: External Memory Interface I/O Restrictions 1.10. Guidelines: Board Design Requirement for DDR2, DDR3, and LPDDR2 1.11. Guidelines: Analog-to-Digital Converter I/O Restriction 1.12. Guidelines: Voltage-Referenced I/O Standards Restriction 1.13. Guidelines: Adhere to the LVDS I/O Restrictions Rules 1.14. Guidelines: Enable Clamp Diode for LVTTL/LVCMOS Input Buffers 1.15. Guidelines: ADC Ground Plane Connection 1.16. Guidelines: Board Design for ADC Reference Voltage Pin 1.17. Guidelines: Board Design for Analog Input 1.18. Guidelines: Board Design for Power Supply Pin and ADC Ground (REFGND) 1.19. Guidelines: MAX® 10 Variable Pitch BGA (VPBGA) Package Overview and Board Fan-Out Recommendations 1.20. Document Revision History for the MAX® 10 FPGA Signal Integrity Design Guidelines
1.4. Guidelines: Clock and Asynchronous Control Input Signal x
1.4.1. Schmitt-Trigger Input Buffer
1.7. Guidelines: Placement Restrictions for 1.0 V I/O Pin x
1.7.1. Calculating the Total Inductance for 1.0 V Pin Placement
1.8. Guidelines: LVTTL/LVCMOS I/O Utilization for MAX® 10 FPGA Package B610 x
1.8.1. GPIO SSO Estimator Tool for MAX® 10 FPGA Package B610
1.8.1. GPIO SSO Estimator Tool for MAX® 10 FPGA Package B610 x
1.8.1.1. GPIO SSO Estimator Tool for MAX® 10 FPGA Package B610 Parameters 1.8.1.2. GPIO SSO Estimator Tool for MAX® 10 FPGA Package B610 Result Analysis 1.8.1.3. GPIO SSO Estimator Tool for MAX® 10 FPGA Package B610 Result Mitigation
1.19. Guidelines: MAX® 10 Variable Pitch BGA (VPBGA) Package Overview and Board Fan-Out Recommendations x
1.19.1. Overview of MAX® 10 VPBGA 1.19.2. MAX® 10 VPBGA Board Fan-Out
1. MAX® 10 FPGA Signal Integrity Design Guidelines

1.7. Guidelines: Placement Restrictions for 1.0 V I/O Pin

To minimize the impact of simultaneous switching noise (SSN) on the I/O pins, ensure that the total mutual inductance (Lm) of the I/O pins in usage surrounding the 1.0 V I/O does not exceed the guidelines in the following table.
Table 3.  Total Lm Guidelines for Pins Surrounding the 1.0 V Pin (Except Package B610)
I/O Standard of Surrounding Pins Locations Relative to 1.0 V Pin Total Lm of Surrounding Pins
1.0 V Within the same bank The total Lm of the surrounding pins in the bank must not exceed 7.41 nH.
In an adjacent bank The total Lm of the surrounding pins in the adjacent bank must not exceed 7.41 nH.
Within the same bank and in an adjacent bank The sum of the total Lm of the surrounding pins in both banks must not exceed 7.41 nH.
Other than 1.0 V In an adjacent bank The total Lm of the surrounding pins in the adjacent bank must not exceed 1 nH.

Example scenarios where the 1.0 V pin is in bank 3 and surrounding pins are in banks 3 and 4:

  • Bank 3 and 4 are both 1.0 V—total Lm of all surrounding pins in both banks must not exceed 7.41 nH.
  • Bank 3 is 1.0 V but bank 4 is 2.5 V—total Lm of surrounding pins in bank 3 must not exceed 7.41 nH and total Lm in bank 4 must not exceed 1 nH.
Table 4.  Total Lm Guidelines for Pins Surrounding the 1.0 V Pin (Package B610 Only)
I/O Standard of Surrounding Pins Locations Relative to 1.0 V Pin Total Lm of Surrounding Pins
1.0 V Within the same bank

To estimate the simultaneous switching output (SSO) noise margin and plan the total 1.0 V utilization in the bank, use the GPIO SSO Estimator Tool for MAX® 10 FPGA Package B610.

In an adjacent bank

Depending on the board thickness, the total Lm of the surrounding pins in the adjacent bank must not exceed:

  • Board thickness ≤ 65 mil—6.91 nH
  • 65 mil < board thickness ≤ 125 mil—4.37 nH
Within the same bank and in an adjacent bank

Depending on the board thickness, the sum of the total Lm of the surrounding pins in both banks must not exceed:

  • Board thickness ≤ 65 mil—6.91 nH
  • 65 mil < board thickness ≤ 125 mil—4.37 nH
Other than 1.0 V In an adjacent bank

Depending on the board thickness, the total Lm of the surrounding pins in the adjacent bank must not exceed:

  • Board thickness ≤ 65 mil—2.03 nH
  • 65 mil < board thickness ≤ 125 mil—0.80 nH

Section Content
Calculating the Total Inductance for 1.0 V Pin Placement

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