1.1. Definitions
1.2. Understanding SSN
1.3. Guidelines: Data Input Pin
1.4. Guidelines: Clock and Asynchronous Control Input Signal
1.5. Guidelines: Clock and Data Input Signal for MAX® 10 E144 Package
1.6. Guidelines: I/O Restriction Rules
1.7. Guidelines: Placement Restrictions for 1.0 V I/O Pin
1.8. Guidelines: LVTTL/LVCMOS I/O Utilization for MAX® 10 FPGA Package B610
1.9. Guidelines: External Memory Interface I/O Restrictions
1.10. Guidelines: Board Design Requirement for DDR2, DDR3, and LPDDR2
1.11. Guidelines: Analog-to-Digital Converter I/O Restriction
1.12. Guidelines: Voltage-Referenced I/O Standards Restriction
1.13. Guidelines: Adhere to the LVDS I/O Restrictions Rules
1.14. Guidelines: Enable Clamp Diode for LVTTL/LVCMOS Input Buffers
1.15. Guidelines: ADC Ground Plane Connection
1.16. Guidelines: Board Design for ADC Reference Voltage Pin
1.17. Guidelines: Board Design for Analog Input
1.18. Guidelines: Board Design for Power Supply Pin and ADC Ground (REFGND)
1.19. Guidelines: MAX® 10 Variable Pitch BGA (VPBGA) Package Overview and Board Fan-Out Recommendations
1.20. Document Revision History for the MAX® 10 FPGA Signal Integrity Design Guidelines
1.8.1. GPIO SSO Estimator Tool for MAX® 10 FPGA Package B610
For the MAX® 10 FPGA package B610, the GPIO SSO Estimator tool calculates the SSO noise margin on a per bank basis, using the same structure for each I/O bank.
In the GPIO SSO Estimator Tool for MAX® 10 FPGA Package B610, set the parameter settings for the LVTTL/LVCMOS output or bidirectional pins in the marked areas, as shown in the following figure.
Figure 7. GPIO SSO Estimator Tool for MAX® 10 FPGA Package B610 StructureThis figure shows the estimator structure for I/O bank 4.
Ensure that you set valid parameter settings. Otherwise, the corresponding Toggling Output I/O Counts cell remains blank and disabled. For example, in the preceding figure, the "fixed" current strength setting is only applicable to 1.0 V LVCMOS.