Intel® MAX® 10 FPGA Signal Integrity Design Guidelines

ID 683572
Date 10/31/2022

Guidelines: Intel® MAX® 10 Board Design Requirement for DDR2, DDR3, and LPDDR2

  • For DDR2, DDR3, and LPDDR2 interfaces, the maximum board skew between pins must be lower than 40 ps. This guideline applies to all pins (address, command, clock, and data).
  • To minimize unwanted inductance from the board via, Intel recommends that you keep the PCB via depth for VCCIO banks below 49.5 mil.
  • For devices with DDR3 interface implementation, onboard termination is required for the DQ, DQS, and address signals. Intel recommends that you use termination resistor value of 80 Ω to VTT.
  • For the DQ, address, and command pins, keep the PCB trace routing length less than six inches for DDR3, or less than three inches for LPDDR2.