MAX® 10 FPGA Signal Integrity Design Guidelines

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ID 683572
Date 3/17/2025
Public
Document Table of Contents
Document Table of Contents x
1. MAX® 10 FPGA Signal Integrity Design Guidelines
1. MAX® 10 FPGA Signal Integrity Design Guidelines x
1.1. Definitions 1.2. Understanding SSN 1.3. Guidelines: Data Input Pin 1.4. Guidelines: Clock and Asynchronous Control Input Signal 1.5. Guidelines: Clock and Data Input Signal for MAX® 10 E144 Package 1.6. Guidelines: I/O Restriction Rules 1.7. Guidelines: Placement Restrictions for 1.0 V I/O Pin 1.8. Guidelines: LVTTL/LVCMOS I/O Utilization for MAX® 10 FPGA Package B610 1.9. Guidelines: External Memory Interface I/O Restrictions 1.10. Guidelines: Board Design Requirement for DDR2, DDR3, and LPDDR2 1.11. Guidelines: Analog-to-Digital Converter I/O Restriction 1.12. Guidelines: Voltage-Referenced I/O Standards Restriction 1.13. Guidelines: Adhere to the LVDS I/O Restrictions Rules 1.14. Guidelines: Enable Clamp Diode for LVTTL/LVCMOS Input Buffers 1.15. Guidelines: ADC Ground Plane Connection 1.16. Guidelines: Board Design for ADC Reference Voltage Pin 1.17. Guidelines: Board Design for Analog Input 1.18. Guidelines: Board Design for Power Supply Pin and ADC Ground (REFGND) 1.19. Guidelines: MAX® 10 Variable Pitch BGA (VPBGA) Package Overview and Board Fan-Out Recommendations 1.20. Document Revision History for the MAX® 10 FPGA Signal Integrity Design Guidelines
1.4. Guidelines: Clock and Asynchronous Control Input Signal x
1.4.1. Schmitt-Trigger Input Buffer
1.7. Guidelines: Placement Restrictions for 1.0 V I/O Pin x
1.7.1. Calculating the Total Inductance for 1.0 V Pin Placement
1.8. Guidelines: LVTTL/LVCMOS I/O Utilization for MAX® 10 FPGA Package B610 x
1.8.1. GPIO SSO Estimator Tool for MAX® 10 FPGA Package B610
1.8.1. GPIO SSO Estimator Tool for MAX® 10 FPGA Package B610 x
1.8.1.1. GPIO SSO Estimator Tool for MAX® 10 FPGA Package B610 Parameters 1.8.1.2. GPIO SSO Estimator Tool for MAX® 10 FPGA Package B610 Result Analysis 1.8.1.3. GPIO SSO Estimator Tool for MAX® 10 FPGA Package B610 Result Mitigation
1.19. Guidelines: MAX® 10 Variable Pitch BGA (VPBGA) Package Overview and Board Fan-Out Recommendations x
1.19.1. Overview of MAX® 10 VPBGA 1.19.2. MAX® 10 VPBGA Board Fan-Out
1. MAX® 10 FPGA Signal Integrity Design Guidelines

1.10. Guidelines: Board Design Requirement for DDR2, DDR3, and LPDDR2

  • For DDR2, DDR3, and LPDDR2 interfaces, the maximum board skew between pins must be lower than 40 ps. This guideline applies to all pins (address, command, clock, and data).
  • To minimize unwanted inductance from the board via, Altera recommends that you keep the PCB via depth for VCCIO banks below 49.5 mil.
  • For devices with DDR3 interface implementation, onboard termination is required for the DQ, DQS, and address signals. Altera recommends that you use termination resistor value of 80 Ω to VTT.
  • For the DQ, address, and command pins, keep the PCB trace routing length less than six inches for DDR3, or less than three inches for LPDDR2.
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