Intel® MAX® 10 FPGA Signal Integrity Design Guidelines

ID 683572
Date 10/31/2022

Guidelines: I/O Restriction Rules

For different I/O standards and conditions, you must limit the number of I/O pins. This I/O restriction rule is applicable if you use LVDS transmitters or receivers. Apply this restriction if one or more LVDS I/O standards reside in the I/O bank.
Table 2.  Maximum Percentage of I/O Pins Allowed for Specific I/O Standards in an I/O BankThis table lists the maximum number of general purpose output pins recommended in a bank in terms of percentage to the total number of I/O pins available in an I/O bank if you use these combinations of I/O standards and conditions.
I/O Standard Condition Max Output Pins Per Bank (%)
2.5 V LVTTL/LVCMOS 16 mA current strength or 25 Ω OCT 25
12 mA current strength 30
8 mA current strength or 50 Ω OCT 45
4 mA current strength 65
2.5 V SSTL 100