Intel® MAX® 10 FPGA Signal Integrity Design Guidelines

ID 683572
Date 10/31/2022

Guidelines: Data Input Pin

For data input signals, fast edge rates cause simultaneously switching input (SSI) noise problem on the wide data bus.

The noise margin is measured at the VIH or VIL instead of the signal edges.

Table 1.  Maximum Recommended Data Input Signal Edge Rate for Intel® MAX® 10 DevicesThis table lists the recommended maximum data input signal edge rate with regards to the percentage of I/O pins usage in an I/O bank.
Percentage of Simultaneous Switching Pins in I/O Bank Recommended Maximum Data Input Signal Edge Rate
50% to 100% 0.6 V/ns
25% to 49% 1.0 V/ns
0% to 24% 1.5 V/ns
Note: If an input pin has an adjacent pin that operates as a toggling output, the edge rate of the input signal to the input pin must be 1.5 V/ns or faster.

If the data input signal exceeds the recommended signal edge rate, you can apply similar approach as the clock input signal to improve the signal integrity.