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1.1. Definitions
1.2. Understanding SSN
1.3. Guidelines: Data Input Pin
1.4. Guidelines: Clock and Asynchronous Control Input Signal
1.5. Guidelines: Clock and Data Input Signal for MAX® 10 E144 Package
1.6. Guidelines: I/O Restriction Rules
1.7. Guidelines: Placement Restrictions for 1.0 V I/O Pin
1.8. Guidelines: LVTTL/LVCMOS I/O Utilization for MAX® 10 FPGA Package B610
1.9. Guidelines: External Memory Interface I/O Restrictions
1.10. Guidelines: Board Design Requirement for DDR2, DDR3, and LPDDR2
1.11. Guidelines: Analog-to-Digital Converter I/O Restriction
1.12. Guidelines: Voltage-Referenced I/O Standards Restriction
1.13. Guidelines: Adhere to the LVDS I/O Restrictions Rules
1.14. Guidelines: Enable Clamp Diode for LVTTL/LVCMOS Input Buffers
1.15. Guidelines: ADC Ground Plane Connection
1.16. Guidelines: Board Design for ADC Reference Voltage Pin
1.17. Guidelines: Board Design for Analog Input
1.18. Guidelines: Board Design for Power Supply Pin and ADC Ground (REFGND)
1.19. Guidelines: MAX® 10 Variable Pitch BGA (VPBGA) Package Overview and Board Fan-Out Recommendations
1.20. Document Revision History for the MAX® 10 FPGA Signal Integrity Design Guidelines
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1.3. Guidelines: Data Input Pin
For data input signals, fast edge rates cause simultaneously switching input (SSI) noise problem on the wide data bus.
The noise margin is measured at the VIH or VIL instead of the signal edges.
Percentage of Simultaneous Switching Pins in I/O Bank | Recommended Maximum Data Input Signal Edge Rate |
---|---|
50% to 100% | 0.6 V/ns |
25% to 49% | 1.0 V/ns |
0% to 24% | 1.5 V/ns |
Note: If an input pin has an adjacent pin that operates as a toggling output, the edge rate of the input signal to the input pin must be 1.5 V/ns or faster.
If the data input signal exceeds the recommended signal edge rate, you can apply similar approach as the clock input signal to improve the signal integrity.
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