MAX® 10 FPGA Signal Integrity Design Guidelines

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ID 683572
Date 3/17/2025
Public
Document Table of Contents
Document Table of Contents x
1. MAX® 10 FPGA Signal Integrity Design Guidelines
1. MAX® 10 FPGA Signal Integrity Design Guidelines x
1.1. Definitions 1.2. Understanding SSN 1.3. Guidelines: Data Input Pin 1.4. Guidelines: Clock and Asynchronous Control Input Signal 1.5. Guidelines: Clock and Data Input Signal for MAX® 10 E144 Package 1.6. Guidelines: I/O Restriction Rules 1.7. Guidelines: Placement Restrictions for 1.0 V I/O Pin 1.8. Guidelines: LVTTL/LVCMOS I/O Utilization for MAX® 10 FPGA Package B610 1.9. Guidelines: External Memory Interface I/O Restrictions 1.10. Guidelines: Board Design Requirement for DDR2, DDR3, and LPDDR2 1.11. Guidelines: Analog-to-Digital Converter I/O Restriction 1.12. Guidelines: Voltage-Referenced I/O Standards Restriction 1.13. Guidelines: Adhere to the LVDS I/O Restrictions Rules 1.14. Guidelines: Enable Clamp Diode for LVTTL/LVCMOS Input Buffers 1.15. Guidelines: ADC Ground Plane Connection 1.16. Guidelines: Board Design for ADC Reference Voltage Pin 1.17. Guidelines: Board Design for Analog Input 1.18. Guidelines: Board Design for Power Supply Pin and ADC Ground (REFGND) 1.19. Guidelines: MAX® 10 Variable Pitch BGA (VPBGA) Package Overview and Board Fan-Out Recommendations 1.20. Document Revision History for the MAX® 10 FPGA Signal Integrity Design Guidelines
1.4. Guidelines: Clock and Asynchronous Control Input Signal x
1.4.1. Schmitt-Trigger Input Buffer
1.7. Guidelines: Placement Restrictions for 1.0 V I/O Pin x
1.7.1. Calculating the Total Inductance for 1.0 V Pin Placement
1.8. Guidelines: LVTTL/LVCMOS I/O Utilization for MAX® 10 FPGA Package B610 x
1.8.1. GPIO SSO Estimator Tool for MAX® 10 FPGA Package B610
1.8.1. GPIO SSO Estimator Tool for MAX® 10 FPGA Package B610 x
1.8.1.1. GPIO SSO Estimator Tool for MAX® 10 FPGA Package B610 Parameters 1.8.1.2. GPIO SSO Estimator Tool for MAX® 10 FPGA Package B610 Result Analysis 1.8.1.3. GPIO SSO Estimator Tool for MAX® 10 FPGA Package B610 Result Mitigation
1.19. Guidelines: MAX® 10 Variable Pitch BGA (VPBGA) Package Overview and Board Fan-Out Recommendations x
1.19.1. Overview of MAX® 10 VPBGA 1.19.2. MAX® 10 VPBGA Board Fan-Out
1. MAX® 10 FPGA Signal Integrity Design Guidelines

1.9. Guidelines: External Memory Interface I/O Restrictions

These I/O rules are applicable if you use external memory interfaces in your design.

Two GPIOs Adjacent to DQ Pin Is Disabled

This limitation is applicable to MAX® 10 10M16, 10M25, 10M40, and 10M50 devices, and only if you use DDR3 and LPDDR2 SDRAM memory standards.

Table 9.  DDR3 and LPDDR2 Memory Interface Widths and Device Packages Where Two GPIOs Adjacent to DQ Pins Are DisabledThis table lists the combination of MAX® 10 10M16, 10M25, 10M40, and 10M50 device packages, and DDR3 and LPDDR2 memory interface widths where you cannot use two GPIO pins that are adjacent to the DQ pins.
Device Package Memory Interface Width (DDR3 and LPPDR2 only)
F256 x8, x16
U324 x8, x16
F484 x8, x16, x24
F672 x8, x16, x24
B610 x8, x16, x24

If you use DDR3 or LPDDR2 SDRAM memory interface standards, the two I/O pins adjacent to the DQ pins are not available for use.

Table 10.  Unavailable I/O Pins While Implementing DDR3 or LPDDR2 External Memory Interfaces in Certain Device Packages—Preliminary
Device Package
F256 U324 F484 B610 F672

10M16

N16

P16

R15

P15

R18

P18

E16

D16

U21

U22

M21

L22

F21

F20

E19

F18

—

—

10M25

N16

P16

—

U21

U22

M21

L22

F21

F20

E19

F18

F17

E17

—

—

10M40

10M50

N16

P16

—

U21

U22

M21

L22

F21

F20

E19

F18

F17

E17

BC40

BC42

AH42

AH41

AF43

AF44

AD36

AD35

E42

E41

R41

R42

N41

N42

B40

A40

W23

W24

U25

U24

T24

R25

R24

P25

K23

K24

J23

H23

G23

F23

G21

G22

Total I/O Utilization in Bank Must Be 75% or Less in Some Devices

If you use DDR3 or LPDDR2 SDRAM memory interface standards, you can generally use 75% of the total number of I/O pins available in I/O banks 5 and 6 for normal I/O operation. This restriction differs from device to device. In some device packages you can use all 100% of the I/Os. The Quartus® Prime software outputs an error message if the restriction rule affects the I/O usage per bank of the device.

If you use DDR2 memory interface standards, you can assign 75% of the available I/O pins in I/O banks 5 and 6 for normal I/O operation. You can assign the remaining 25% of the I/O pins as input pins only.

For more information about DDR2, DDR3, and LPPDR2 board design requirement, refer to the related information.

Related Information
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