Visible to Intel only — GUID: rzj1741070750728
Ixiasoft
Visible to Intel only — GUID: rzj1741070750728
Ixiasoft
1.9. Guidelines: External Memory Interface I/O Restrictions
Two GPIOs Adjacent to DQ Pin Is Disabled
This limitation is applicable to MAX® 10 10M16, 10M25, 10M40, and 10M50 devices, and only if you use DDR3 and LPDDR2 SDRAM memory standards.
Device Package | Memory Interface Width (DDR3 and LPPDR2 only) |
---|---|
F256 | x8, x16 |
U324 | x8, x16 |
F484 | x8, x16, x24 |
F672 | x8, x16, x24 |
B610 | x8, x16, x24 |
If you use DDR3 or LPDDR2 SDRAM memory interface standards, the two I/O pins adjacent to the DQ pins are not available for use.
Device | Package | ||||
---|---|---|---|---|---|
F256 | U324 | F484 | B610 | F672 | |
10M16 |
N16 P16 |
R15 P15 R18 P18 E16 D16 |
U21 U22 M21 L22 F21 F20 E19 F18 |
— |
— |
10M25 |
N16 P16 |
— |
U21 U22 M21 L22 F21 F20 E19 F18 F17 E17 |
— |
— |
10M40 10M50 |
N16 P16 |
— |
U21 U22 M21 L22 F21 F20 E19 F18 F17 E17 |
BC40 BC42 AH42 AH41 AF43 AF44 AD36 AD35 E42 E41 R41 R42 N41 N42 B40 A40 |
W23 W24 U25 U24 T24 R25 R24 P25 K23 K24 J23 H23 G23 F23 G21 G22 |
Total I/O Utilization in Bank Must Be 75% or Less in Some Devices
If you use DDR3 or LPDDR2 SDRAM memory interface standards, you can generally use 75% of the total number of I/O pins available in I/O banks 5 and 6 for normal I/O operation. This restriction differs from device to device. In some device packages you can use all 100% of the I/Os. The Quartus® Prime software outputs an error message if the restriction rule affects the I/O usage per bank of the device.
If you use DDR2 memory interface standards, you can assign 75% of the available I/O pins in I/O banks 5 and 6 for normal I/O operation. You can assign the remaining 25% of the I/O pins as input pins only.
For more information about DDR2, DDR3, and LPPDR2 board design requirement, refer to the related information.