1.1. Definitions
1.2. Understanding SSN
1.3. Guidelines: Data Input Pin
1.4. Guidelines: Clock and Asynchronous Control Input Signal
1.5. Guidelines: Clock and Data Input Signal for MAX® 10 E144 Package
1.6. Guidelines: I/O Restriction Rules
1.7. Guidelines: Placement Restrictions for 1.0 V I/O Pin
1.8. Guidelines: LVTTL/LVCMOS I/O Utilization for MAX® 10 FPGA Package B610
1.9. Guidelines: External Memory Interface I/O Restrictions
1.10. Guidelines: Board Design Requirement for DDR2, DDR3, and LPDDR2
1.11. Guidelines: Analog-to-Digital Converter I/O Restriction
1.12. Guidelines: Voltage-Referenced I/O Standards Restriction
1.13. Guidelines: Adhere to the LVDS I/O Restrictions Rules
1.14. Guidelines: Enable Clamp Diode for LVTTL/LVCMOS Input Buffers
1.15. Guidelines: ADC Ground Plane Connection
1.16. Guidelines: Board Design for ADC Reference Voltage Pin
1.17. Guidelines: Board Design for Analog Input
1.18. Guidelines: Board Design for Power Supply Pin and ADC Ground (REFGND)
1.19. Guidelines: MAX® 10 Variable Pitch BGA (VPBGA) Package Overview and Board Fan-Out Recommendations
1.20. Document Revision History for the MAX® 10 FPGA Signal Integrity Design Guidelines
1.8.1.2. GPIO SSO Estimator Tool for MAX® 10 FPGA Package B610 Result Analysis
After you specify the parameter settings, the GPIO SSO Estimator Tool for MAX® 10 FPGA Package B610 displays the analysis results.
Field | Description |
---|---|
SSO Noise Margin (%) | Displays the SSO noise margin in percentage, based on the combination of parameters. Other values:
Ensure that the reported SSO noise margin for the I/O bank is higher than 0%. |
Assigned IO Counts | Displays the total number of simultaneous toggling outputs you specified for the I/O bank. Other value:
Ensure that the displayed value is not higher than the Total Available IOs value. |
Total Available IOs | Displays the total available I/Os in the I/O bank. |
Result | Displays the analysis result based on the SSO Noise Margin (%) and Assigned IO Counts values:
|
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