MAX® 10 FPGA Signal Integrity Design Guidelines

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ID 683572
Date 3/17/2025
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Document Table of Contents
Document Table of Contents x
1. MAX® 10 FPGA Signal Integrity Design Guidelines
1. MAX® 10 FPGA Signal Integrity Design Guidelines x
1.1. Definitions 1.2. Understanding SSN 1.3. Guidelines: Data Input Pin 1.4. Guidelines: Clock and Asynchronous Control Input Signal 1.5. Guidelines: Clock and Data Input Signal for MAX® 10 E144 Package 1.6. Guidelines: I/O Restriction Rules 1.7. Guidelines: Placement Restrictions for 1.0 V I/O Pin 1.8. Guidelines: LVTTL/LVCMOS I/O Utilization for MAX® 10 FPGA Package B610 1.9. Guidelines: External Memory Interface I/O Restrictions 1.10. Guidelines: Board Design Requirement for DDR2, DDR3, and LPDDR2 1.11. Guidelines: Analog-to-Digital Converter I/O Restriction 1.12. Guidelines: Voltage-Referenced I/O Standards Restriction 1.13. Guidelines: Adhere to the LVDS I/O Restrictions Rules 1.14. Guidelines: Enable Clamp Diode for LVTTL/LVCMOS Input Buffers 1.15. Guidelines: ADC Ground Plane Connection 1.16. Guidelines: Board Design for ADC Reference Voltage Pin 1.17. Guidelines: Board Design for Analog Input 1.18. Guidelines: Board Design for Power Supply Pin and ADC Ground (REFGND) 1.19. Guidelines: MAX® 10 Variable Pitch BGA (VPBGA) Package Overview and Board Fan-Out Recommendations 1.20. Document Revision History for the MAX® 10 FPGA Signal Integrity Design Guidelines
1.4. Guidelines: Clock and Asynchronous Control Input Signal x
1.4.1. Schmitt-Trigger Input Buffer
1.7. Guidelines: Placement Restrictions for 1.0 V I/O Pin x
1.7.1. Calculating the Total Inductance for 1.0 V Pin Placement
1.8. Guidelines: LVTTL/LVCMOS I/O Utilization for MAX® 10 FPGA Package B610 x
1.8.1. GPIO SSO Estimator Tool for MAX® 10 FPGA Package B610
1.8.1. GPIO SSO Estimator Tool for MAX® 10 FPGA Package B610 x
1.8.1.1. GPIO SSO Estimator Tool for MAX® 10 FPGA Package B610 Parameters 1.8.1.2. GPIO SSO Estimator Tool for MAX® 10 FPGA Package B610 Result Analysis 1.8.1.3. GPIO SSO Estimator Tool for MAX® 10 FPGA Package B610 Result Mitigation
1.19. Guidelines: MAX® 10 Variable Pitch BGA (VPBGA) Package Overview and Board Fan-Out Recommendations x
1.19.1. Overview of MAX® 10 VPBGA 1.19.2. MAX® 10 VPBGA Board Fan-Out
1. MAX® 10 FPGA Signal Integrity Design Guidelines

1.8.1.1. GPIO SSO Estimator Tool for MAX® 10 FPGA Package B610 Parameters

The GPIO SSO Estimator Tool for MAX® 10 FPGA Package B610 has prefilled and non-editable parameters and parameter settings you must specify for the I/O banks you use.
Table 7.   GPIO SSO Estimator Tool for MAX® 10 FPGA Package B610 Parameter Settings
Parameter Allowed Values Description
Board Thickness
  • Thin
  • Thick

Specify the board thickness:

  • Thin—thickness ≤ 65 mil
  • Thick—65 mil < thickness ≤ 125 mil
I/O Bank
  • 1A
  • 1B
  • 2 to 8

This parameter is prefilled and not editable.
Voltage (V)
  • 1
  • 1.2
  • 1.5
  • 1.8
  • 2.5
  • 3
  • 3.3

Specify the voltage for the I/O bank.
Drive Strength
  • 16 mA
  • 12 mA
  • 10 mA
  • 8 mA
  • 6 mA
  • 4 mA
  • 2 mA
  • oct_25
  • oct_50
  • fixed

This parameter is prefilled and not editable.

Note: The "fixed" drive strength setting applies only to the 1.0 V LVCMOS I/O standard. This I/O standard does not support the programmable current strength and OCT features.
IO Standard
  • LVCMOS
  • LVTTL
 Specify the I/O standard for the output.
Slew Rate
  • Slow
  • Medium
  • Fast
 Specify the slew rate setting for the output.
Series Termination (Yes/No)
  • Yes
  • No

Specify whether you want to add a 30 Ω on-board series resistor at the receiver side.

  • Yes—the SSO noise margin calculation considers the series resistor.
  • No—the SSO noise margin calculation does not include the series resistor.
  • Note: Altera recommends that you perform IBIS or SPICE simulations to determine the suitable series resistor value for your specific application.
Toggling Output IO Counts —

Specify the I/O counts of simultaneous toggling output you use in the I/O bank.

Note: By default, this setting is disabled. The setting becomes editable after you set valid values for the other parameters.
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