MAX® 10 FPGA Signal Integrity Design Guidelines

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ID 683572
Date 3/17/2025
Public
Document Table of Contents
Document Table of Contents x
1. MAX® 10 FPGA Signal Integrity Design Guidelines
1. MAX® 10 FPGA Signal Integrity Design Guidelines x
1.1. Definitions 1.2. Understanding SSN 1.3. Guidelines: Data Input Pin 1.4. Guidelines: Clock and Asynchronous Control Input Signal 1.5. Guidelines: Clock and Data Input Signal for MAX® 10 E144 Package 1.6. Guidelines: I/O Restriction Rules 1.7. Guidelines: Placement Restrictions for 1.0 V I/O Pin 1.8. Guidelines: LVTTL/LVCMOS I/O Utilization for MAX® 10 FPGA Package B610 1.9. Guidelines: External Memory Interface I/O Restrictions 1.10. Guidelines: Board Design Requirement for DDR2, DDR3, and LPDDR2 1.11. Guidelines: Analog-to-Digital Converter I/O Restriction 1.12. Guidelines: Voltage-Referenced I/O Standards Restriction 1.13. Guidelines: Adhere to the LVDS I/O Restrictions Rules 1.14. Guidelines: Enable Clamp Diode for LVTTL/LVCMOS Input Buffers 1.15. Guidelines: ADC Ground Plane Connection 1.16. Guidelines: Board Design for ADC Reference Voltage Pin 1.17. Guidelines: Board Design for Analog Input 1.18. Guidelines: Board Design for Power Supply Pin and ADC Ground (REFGND) 1.19. Guidelines: MAX® 10 Variable Pitch BGA (VPBGA) Package Overview and Board Fan-Out Recommendations 1.20. Document Revision History for the MAX® 10 FPGA Signal Integrity Design Guidelines
1.4. Guidelines: Clock and Asynchronous Control Input Signal x
1.4.1. Schmitt-Trigger Input Buffer
1.7. Guidelines: Placement Restrictions for 1.0 V I/O Pin x
1.7.1. Calculating the Total Inductance for 1.0 V Pin Placement
1.8. Guidelines: LVTTL/LVCMOS I/O Utilization for MAX® 10 FPGA Package B610 x
1.8.1. GPIO SSO Estimator Tool for MAX® 10 FPGA Package B610
1.8.1. GPIO SSO Estimator Tool for MAX® 10 FPGA Package B610 x
1.8.1.1. GPIO SSO Estimator Tool for MAX® 10 FPGA Package B610 Parameters 1.8.1.2. GPIO SSO Estimator Tool for MAX® 10 FPGA Package B610 Result Analysis 1.8.1.3. GPIO SSO Estimator Tool for MAX® 10 FPGA Package B610 Result Mitigation
1.19. Guidelines: MAX® 10 Variable Pitch BGA (VPBGA) Package Overview and Board Fan-Out Recommendations x
1.19.1. Overview of MAX® 10 VPBGA 1.19.2. MAX® 10 VPBGA Board Fan-Out
1. MAX® 10 FPGA Signal Integrity Design Guidelines

1.12. Guidelines: Voltage-Referenced I/O Standards Restriction

These restrictions apply if you use the VREF pin.
  • If you use a shared VREF pin as an I/O, all voltage-reference input buffers (SSTL, HSTL, and HSUL) are disabled.
  • If you use a shared VREF pin as a voltage reference, you must enable the input buffer of specific I/O pin to use the voltage-reference I/O standards.
  • The voltage-referenced I/O standards are not supported in the following I/O banks of these device packages:
    • All I/O banks of V36 package of 10M02.
    • All I/O banks of V81 package of 10M08.
    • Banks 1A and 1B of E144 package of 10M50.
  • For devices with banks 1A and 1B, if you use the VREF pin, you must supply a common VCCIO to banks 1A and 1B.
  • The maximum number of voltage-referenced inputs for each VREF pin is 75% of the total number of I/O pads. The Quartus® Prime software warns you if you exceed the maximum number.
  • Except for I/O pins that you used for static signals, all non-voltage-referenced output must be placed two pads away from a VREF pin. The Quartus® Prime software outputs an error message if this rule is violated.
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