Intel® MAX® 10 FPGA Signal Integrity Design Guidelines

ID 683572
Date 10/31/2022

Guidelines: Voltage-Referenced I/O Standards Restriction

These restrictions apply if you use the VREF pin.
  • If you use a shared VREF pin as an I/O, all voltage-reference input buffers (SSTL, HSTL, and HSUL) are disabled.
  • If you use a shared VREF pin as a voltage reference, you must enable the input buffer of specific I/O pin to use the voltage-reference I/O standards.
  • The voltage-referenced I/O standards are not supported in the following I/O banks of these device packages:
    • All I/O banks of V36 package of 10M02.
    • All I/O banks of V81 package of 10M08.
    • Banks 1A and 1B of E144 package of 10M50.
  • For devices with banks 1A and 1B, if you use the VREF pin, you must supply a common VCCIO to banks 1A and 1B.
  • The maximum number of voltage-referenced inputs for each VREF pin is 75% of the total number of I/O pads. The Intel® Quartus® Prime software warns you if you exceed the maximum number.
  • Except for I/O pins that you used for static signals, all non-voltage-referenced output must be placed two pads away from a VREF pin. The Intel® Quartus® Prime software will output an error message if this rule is violated.