Interfacing Intel® FPGA Devices with 3.3/3.0/2.5 V LVTTL/LVCMOS I/O Systems
To manage signal integrity issues and protect the input pin, follow the guidelines in this document if you interface 3.3 V, 3.0 V, 2.5 V LVTTL or LVCMOS I/O systems with these Intel® device families:
- Cyclone® III
- Cyclone® IV
- Intel® Cyclone® 10 LP
- Intel® MAX® 10
To ensure device reliability and proper operation, you must design the I/O interfaces within the specifications recommended by the guidelines in this document.
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