AN 447: Interfacing Intel® FPGA Devices with 3.3/3.0/2.5 V LVTTL/LVCMOS I/O Systems

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ID 683295
Date 3/28/2022
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Document Table of Contents x
Interfacing Intel® FPGA Devices with 3.3/3.0/2.5 V LVTTL/LVCMOS I/O Systems
Interfacing Intel® FPGA Devices with 3.3/3.0/2.5 V LVTTL/LVCMOS I/O Systems x
Receiver Level Requirements Guideline: Use Internal PCI Clamp Diode on the Pin Guideline: Use Series Termination Resistor Guideline: Select Appropriate Driver Interface Current between Supported Intel® Devices Document Revision History for AN 447: Interfacing Intel FPGA Devices with 3.3/3.0/2.5 V LVTTL/LVCMOS I/O Systems
Guideline: Use Internal PCI Clamp Diode on the Pin x
Measuring DC Current with PCI Clamp Diode
Guideline: Use Series Termination Resistor x
Selecting Appropriate Series Termination Resistor Value Example of Determining Series Termination Resistor Value
Guideline: Select Appropriate Driver x
Driver Selection Reference Current Limits Measurement Examples Evaluating Interface Using Driver Selection Method
Interfacing Intel® FPGA Devices with 3.3/3.0/2.5 V LVTTL/LVCMOS I/O Systems

Guideline: Select Appropriate Driver

The output characteristics of a driver determines how much overshoot voltage is seen at the receiver when the interface is not terminated. You can address signal integrity concerns in your interface by selecting the appropriate driver.

You must select a driver that meets the current limits of the supported Intel® device at the appropriate points in the I/V curve. You can obtain the I/V curve of the driver from the IBIS file provided by the device manufacturer.

You can also use slew rate control, if it is available on the driver, to address signal integrity concerns. Slew rate control allows you to reduce the edge rate of the output signal to help control voltage overshoot at the receiver. You must perform simulations to ensure that the specifications are met when using the slew rate feature.

Level Two Title