Intel® MAX® 10 FPGA Device Architecture

ID 683105
Date 10/31/2022
Document Table of Contents

1. Intel® MAX® 10 FPGA Device Architecture

The Intel® MAX® 10 devices consist of the following:

  • Logic array blocks (LABs)
  • Analog-to-digital converter (ADC)
  • User flash memory (UFM)
  • Embedded multiplier blocks
  • Embedded memory blocks (M9K)
  • Clocks and phase-locked loops (PLL)
  • General purpose I/O
  • High-speed LVDS I/O
  • External memory interfaces
  • Configuration flash memory (CFM)
Figure 1. Typical Device Floorplan for Intel® MAX® 10 Devices
  • The amount and location of each block varies in each Intel® MAX® 10 device.
  • Certain Intel® MAX® 10 devices may not contain a specific block.

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