Visible to Intel only — GUID: sss1396937447501
Ixiasoft
1.1. Logic Array Block
1.2. Embedded Memory
1.3. Embedded Multiplier
1.4. Clocking and PLL
1.5. General Purpose I/O
1.6. High-Speed LVDS I/O
1.7. External Memory Interface
1.8. Analog to Digital Converter
1.9. Configuration Schemes
1.10. User Flash Memory
1.11. Power Management
1.12. Document Revision History for Intel® MAX® 10 FPGA Device Architecture
Visible to Intel only — GUID: sss1396937447501
Ixiasoft
1.6. High-Speed LVDS I/O
The Intel® MAX® 10 device family supports high-speed LVDS protocols through the LVDS I/O banks and the Soft LVDS Intel® FPGA IP.
The Intel® MAX® 10 devices use registers and logic in the core fabric to implement LVDS input and output interfaces.
- For LVDS transmitters and receivers, Intel® MAX® 10 devices use the double data rate I/O (DDIO) registers that reside in the I/O elements (IOE). This architecture improves performance with regards to the receiver input skew margin (RSKM) or transmitter channel-to-channel skew (TCCS).
- For the LVDS serializer/deserializer (SERDES), Intel® MAX® 10 devices use logic elements (LE) registers.
Related Information