Intel® MAX® 10 FPGA Device Architecture

ID 683105
Date 10/31/2022
Public
Document Table of Contents

1.6. High-Speed LVDS I/O

The Intel® MAX® 10 device family supports high-speed LVDS protocols through the LVDS I/O banks and the Soft LVDS Intel® FPGA IP.

The Intel® MAX® 10 devices use registers and logic in the core fabric to implement LVDS input and output interfaces.

  • For LVDS transmitters and receivers, Intel® MAX® 10 devices use the double data rate I/O (DDIO) registers that reside in the I/O elements (IOE). This architecture improves performance with regards to the receiver input skew margin (RSKM) or transmitter channel-to-channel skew (TCCS).
  • For the LVDS serializer/deserializer (SERDES), Intel® MAX® 10 devices use logic elements (LE) registers.