Intel® MAX® 10 FPGA Device Architecture

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ID 683105
Date 10/31/2022
Public
Document Table of Contents
Document Table of Contents x
1. Intel® MAX® 10 FPGA Device Architecture
1. Intel® MAX® 10 FPGA Device Architecture x
1.1. Logic Array Block 1.2. Embedded Memory 1.3. Embedded Multiplier 1.4. Clocking and PLL 1.5. General Purpose I/O 1.6. High-Speed LVDS I/O 1.7. External Memory Interface 1.8. Analog to Digital Converter 1.9. Configuration Schemes 1.10. User Flash Memory 1.11. Power Management 1.12. Document Revision History for Intel® MAX® 10 FPGA Device Architecture
1.1. Logic Array Block x
1.1.1. LAB Interconnects 1.1.2. LAB Control Signals 1.1.3. Logic Elements
1.1.3. Logic Elements x
1.1.3.1. LE Features 1.1.3.2. LE Operating Modes
1.1.3.2. LE Operating Modes x
1.1.3.2.1. Normal Mode 1.1.3.2.2. Arithmetic Mode
1.3. Embedded Multiplier x
1.3.1. 18-Bit Multipliers 1.3.2. 9-Bit Multipliers
1.4. Clocking and PLL x
1.4.1. Global Clock Networks 1.4.2. Internal Oscillator 1.4.3. PLL Block and Locations
1.5. General Purpose I/O x
1.5.1. Intel® MAX® 10 I/O Banks Architecture 1.5.2. Intel® MAX® 10 I/O Banks Locations
1.6. High-Speed LVDS I/O x
1.6.1. Intel® MAX® 10 High-Speed LVDS Circuitry 1.6.2. Intel® MAX® 10 High-Speed LVDS I/O Location
1.7. External Memory Interface x
1.7.1. Intel® MAX® 10 I/O Banks for External Memory Interface
1.8. Analog to Digital Converter x
1.8.1. ADC Block Locations
1.9. Configuration Schemes x
1.9.1. JTAG Configuration 1.9.2. Internal Configuration
1.11. Power Management x
1.11.1. Single-Supply Device 1.11.2. Dual-Supply Device 1.11.3. Power Management Controller Scheme 1.11.4. Hot Socketing
1. Intel® MAX® 10 FPGA Device Architecture

1.8. Analog to Digital Converter

Intel® MAX® 10 devices feature up to two analog-to-digital converters (ADC). The ADCs provide the Intel® MAX® 10 devices with built-in capability for on-die temperature monitoring and external analog signal conversion.

The ADC solution consists of hard IP blocks in the Intel® MAX® 10 device periphery and soft logic through the Modular ADC Core Intel® FPGA IP and Modular Dual ADC Core Intel® FPGA IP.

The ADC solution provides you with built-in capability to translate analog quantities to digital data for information processing, computing, data transmission, and control systems. The basic function is to provide a 12 bit digital representation of the analog signal being observed.

The ADC solution works in two modes:

  • Normal mode—monitors single-ended external inputs with a cumulative sampling rate of up to 1 million samples per second (MSPS):
    • Single ADC devices—up to 17 single-ended external inputs (one dedicated analog and 16 dual function input pins)
    • Dual ADC devices—up to 18 single-ended external inputs (one dedicated analog and eight dual function input pins in each ADC block)
  • Temperature sensing mode—monitors external temperature data input with a sampling rate of up to 50 kilosamples per second. In dual ADC devices, only the first ADC block supports this mode.
Figure 26.  ADC Hard IP Block in Intel® MAX® 10 Devices

Section Content
ADC Block Locations

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