Intel® MAX® 10 FPGA Device Architecture

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ID 683105
Date 10/31/2022
Public
Document Table of Contents
Document Table of Contents x
1. Intel® MAX® 10 FPGA Device Architecture
1. Intel® MAX® 10 FPGA Device Architecture x
1.1. Logic Array Block 1.2. Embedded Memory 1.3. Embedded Multiplier 1.4. Clocking and PLL 1.5. General Purpose I/O 1.6. High-Speed LVDS I/O 1.7. External Memory Interface 1.8. Analog to Digital Converter 1.9. Configuration Schemes 1.10. User Flash Memory 1.11. Power Management 1.12. Document Revision History for Intel® MAX® 10 FPGA Device Architecture
1.1. Logic Array Block x
1.1.1. LAB Interconnects 1.1.2. LAB Control Signals 1.1.3. Logic Elements
1.1.3. Logic Elements x
1.1.3.1. LE Features 1.1.3.2. LE Operating Modes
1.1.3.2. LE Operating Modes x
1.1.3.2.1. Normal Mode 1.1.3.2.2. Arithmetic Mode
1.3. Embedded Multiplier x
1.3.1. 18-Bit Multipliers 1.3.2. 9-Bit Multipliers
1.4. Clocking and PLL x
1.4.1. Global Clock Networks 1.4.2. Internal Oscillator 1.4.3. PLL Block and Locations
1.5. General Purpose I/O x
1.5.1. Intel® MAX® 10 I/O Banks Architecture 1.5.2. Intel® MAX® 10 I/O Banks Locations
1.6. High-Speed LVDS I/O x
1.6.1. Intel® MAX® 10 High-Speed LVDS Circuitry 1.6.2. Intel® MAX® 10 High-Speed LVDS I/O Location
1.7. External Memory Interface x
1.7.1. Intel® MAX® 10 I/O Banks for External Memory Interface
1.8. Analog to Digital Converter x
1.8.1. ADC Block Locations
1.9. Configuration Schemes x
1.9.1. JTAG Configuration 1.9.2. Internal Configuration
1.11. Power Management x
1.11.1. Single-Supply Device 1.11.2. Dual-Supply Device 1.11.3. Power Management Controller Scheme 1.11.4. Hot Socketing
1. Intel® MAX® 10 FPGA Device Architecture

1.6.2. Intel® MAX® 10 High-Speed LVDS I/O Location

All I/O banks in Intel® MAX® 10 devices support 2.5 V true LVDS input and 2.5 V emulated LVDS output. The high-speed I/O banks also support 1.8 V true LVDS input. Only the bottom I/O banks support 2.5 V and 1.8 V true LVDS outputs.
Note: The 1.8 V LVDS buffers are supported as inputs on all high-speed I/O banks but as outputs only on the bottom banks. The low-speed and high-speed DDR3 I/O banks do not support 1.8 V LVDS. The 1.8 V LVDS I/O standard is supported in industrial- and commercial-grade Intel® MAX® 10 dual supply devices except in packages V36 and V81. Refer to the related information.
Figure 21. LVDS Support in I/O Banks of 10M02 Devices (Except Single Power Supply U324 Package)This figure shows a top view of the silicon die. Each bank is labeled with the actual bank number. LVPECL support only in banks 2 and 6.


Figure 22. LVDS Support in I/O Banks of 10M02 (Single Power Supply U324 Package), 10M04, and 10M08 (Except V81, M153, and U169 Packages) DevicesThis figure shows a top view of the silicon die. Each bank is labeled with the actual bank number. LVPECL support only in banks 2 and 6.


Figure 23. LVDS Support in I/O Banks of 10M08 V81, M153, and U169 Packages Devices
Figure 24. LVDS Support in I/O Banks of 10M16, 10M25, 10M40, and 10M50 DevicesThis figure shows a top view of the silicon die. Each bank is labeled with the actual bank number. LVPECL support only in banks 2, 3, 6, and 8.


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