I/O PLL Reconfiguration and Dynamic Phase Shift for Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices
Intel® Arria® 10 and Intel® Cyclone® 10 GX I/O PLL supports dynamic reconfiguration when the device is in user mode. With the dynamic reconfiguration feature, you can reconfigure I/O PLL settings in real time. You can change the divide settings of the PLL counters and the PLL bandwidth settings (loop filter setting and charge pump setting) through an Avalon® memory-mapped interface in the PLL Reconfig Intel® FPGA IP core, without the need to reconfigure the entire FPGA. Intel® Arria® 10 and Intel® Cyclone® 10 GX I/O PLL uses divide counters (N, M, and C counters) and a voltage-controlled oscillator (VCO) to synthesize the desired phase and frequency output.
You can perform dynamic reconfiguration using one of the following methods:
- Memory Initialization File (.mif) streaming reconfiguration
- Allows I/O PLL reconfiguration using predefined settings saved in an on-chip ROM. You can store many unique PLL configurations in a single ROM.
- The .mif file is generated automatically by the IOPLL Intel® FPGA IP core. Using the generated .mif file during .mif streaming reconfiguration ensures the legality of the new configuration.
- Intel recommends using this reconfiguration method.
- Reconfiguration of individual PLL settings
- Supports N, M, and C counters reconfiguration.
- Supports bandwidth setting changes of the loop filter configuration. You must reconfigure the charge pump current setting and loop filter resistance setting for stable operation of the PLL if the M counter value is changed.
- Supports both read and write operations.
- This method of reconfiguration is for advanced users. You must ensure the reconfigured PLL settings are within the legal range.
With the dynamic phase shift feature of the I/O PLL, you can modify the phase of the PLL output clocks in real time. You can adjust the phase in increments of 1/8 of the VCO period.
You can perform dynamic phase shift using one of the following methods:
- Direct access to the dynamic phase shift ports in the IOPLL IP core
- Supports both shift up and shift down operations.
- Supports up to seven phase shift steps in a single operation.
- Dynamic phase shift via the PLL Reconfig IP core
- Available via .mif streaming reconfiguration or via reconfiguration of individual PLL settings.
- Supports only write operation.
Did you find the information on this page useful?