AN 728: I/O PLL Reconfiguration and Dynamic Phase Shift for Intel® Arria® 10 and Intel Cyclone® 10 GX Devices

ID 683845
Date 8/08/2022
Document Table of Contents

Dynamic Phase Shift Ports in the IOPLL IP Core

Figure 3. Dynamic Phase Shift Port Ports in the IOPLL IP Core
Table 8.  Dynamic Phase Shift Ports in the IOPLL IP Core
Port Direction Description
scanclk Input Dynamic phase shift clock that drives the IOPLL IP core dynamic phase shift operation. This port must be connected to a valid clock source. The maximum input clock frequency is 100 MHz.
phase_en Input Active high signal. Asserts to start the dynamic phase shift operation.
updn Input Determines the direction of dynamic phase shift. When updn = 0, phase shift is in negative direction (shift down). When updn = 1, phase shift is in positive direction (shift up).
cntsel[4..0] Input
Determines the counter to be selected to perform dynamic phase shift operation.
Counter Name cntsel[4..0] (Binary)
C0 5’b00000
C1 5’b00001
C2 5’b00010
C3 5’b00011
C4 5’b00100
C5 5’b00101
C6 5’b00110
C7 5’b00111
C8 5’b01000
All C counters 5’b01111
num_phase_shift[2..0] Input Determines the number of phase shifts per dynamic phase shift operation. Up to seven phase shifts per operation are possible. Each phase shift step is equal to 1/8 of I/O PLL VCO period.
phase_done Output The IOPLL IP core drives this port high for one scanclk cycle after dynamic phase shift operation is complete.