AN 728: I/O PLL Reconfiguration and Dynamic Phase Shift for Intel® Arria® 10 and Intel Cyclone® 10 GX Devices

ID 683845
Date 8/08/2022
Document Table of Contents

Address Bus and Data Bus Setting for Dynamic Phase Shift

Table 3.  Address Bus and Data Bus Bit Setting for Dynamic Phase Shift using the PLL Reconfig IP Core
Counter Name Address Bus Bit Setting (Binary) Data Bus Bit Setting (Binary)
C0 9’b100000000
  • Data[2..0] = number of phase shift
    • Maximum of seven phase shifts per operation. Each phase shift step is equal to 1/8 of I/O PLL VCO period.
  • Data[3] = direction of phase shift
    • When Data[3] = 0, phase shift is in negative direction (shift down).
    • When Data[3] = 1, phase shift is in positive direction (shift up).
C1 9’b100000001
C2 9’b100000010
C3 9’b100000011
C4 9’b100000100
C5 9’b100000101
C6 9’b100000110
C7 9’b100000111
C8 9’b100001000
All C counters 9’b100001111