AN 728: I/O PLL Reconfiguration and Dynamic Phase Shift for Intel® Arria® 10 and Intel Cyclone® 10 GX Devices

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ID 683845
Date 8/08/2022
Public
Document Table of Contents
Document Table of Contents x
I/O PLL Reconfiguration and Dynamic Phase Shift for Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices
I/O PLL Reconfiguration and Dynamic Phase Shift for Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices x
Implementing I/O PLL Reconfiguration in the PLL Reconfig IP Core Implementing I/O PLL Dynamic Phase Shift in the IOPLL IP Core Design Considerations Using the Design Examples Document Revision History for AN 728: I/O PLL Reconfiguration and Dynamic Phase Shift for Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices
Implementing I/O PLL Reconfiguration in the PLL Reconfig IP Core x
Avalon® Memory-Mapped Interface Ports in the PLL Reconfig IP Core Connecting the IOPLL and PLL Reconfig IP Cores Connectivity between the IOPLL and PLL Reconfig IP Cores I/O PLL Reconfiguration Write Operation I/O PLL Reconfiguration Read Operation Address Bus and Data Bus Settings .mif Streaming Reconfiguration
I/O PLL Reconfiguration Write Operation x
Write Operation for .mif Streaming Reconfiguration
Address Bus and Data Bus Settings x
Address Bus and Data Bus Setting for Counter Setting Reconfiguration Address Bus and Data Bus Setting for Dynamic Phase Shift Address Bus and Data Bus Setting for Bandwidth Setting Reconfiguration Data Bus Setting for Loop Filter and Charge Pump Settings Address Bus and Data Bus Setting for .mif Streaming Reconfiguration
.mif Streaming Reconfiguration x
.mif File Format .mif Streaming Reconfiguration Operation Codes
Implementing I/O PLL Dynamic Phase Shift in the IOPLL IP Core x
Dynamic Phase Shift Ports in the IOPLL IP Core I/O PLL Dynamic Phase Shift Operation
Using the Design Examples x
Design Example 1: I/O PLL Reconfiguration Design Example 2: .mif Streaming Reconfiguration Design Example 3: I/O PLL Dynamic Phase Shift
I/O PLL Reconfiguration and Dynamic Phase Shift for Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices

Design Example 1: I/O PLL Reconfiguration

The design example uses a 10AX115R2F40I2SGE2 device to demonstrate the implementation of the I/O PLL dynamic reconfiguration using the PLL Reconfig IP core. This design example consists of the IOPLL IP core, PLL Reconfig IP core, and In-System Sources & Probes Intel® FPGA IP core.

The I/O PLL synthesizes two output clocks of 400 MHz with 0 ps phase shift and 200 MHz with 0 ps phase shift on counter C0 output and counter C1 output respectively at medium bandwidth. The input reference clock is 50 MHz.

The PLL Reconfig IP core connects to a state machine to perform I/O PLL reconfiguration operation. A low pulse on the reset_SM input through the In-System Sources & Probes IP core triggers the I/O PLL reconfiguration operation. After I/O PLL reconfiguration operation is complete, the I/O PLL operates in the following configuration at medium bandwidth:

  • 100 MHz with 0 ps phase shift on counter C0 output
  • 100 MHz with 312 ps phase shift on counter C1 output

To run the test with the design example, perform these steps:

  1. Download and restore the an728-iopll-reconfig-general.qar file.
  2. If necessary, change the device and pin assignments (refclk, c0_out, c1_out, and locked pins) of the design example to match your hardware.
  3. Recompile the design example. Ensure that the design example does not contain any timing violation after recompilation.
  4. Open the AN.spf and program the device with test.sof.
  5. Assert a high pulse on reset_reconfig signal to reset the PLL Reconfig IP core. Then assert a high pulse on reset_SM signal to start the I/O PLL dynamic reconfiguration operation.
Figure 4. Waveform Example for I/O PLL Reconfiguration Design Example
Level Two Title