AN 728: I/O PLL Reconfiguration and Dynamic Phase Shift for Intel® Arria® 10 and Intel Cyclone® 10 GX Devices

ID 683845
Date 8/08/2022
Document Table of Contents

Design Considerations

Resetting the PLL

  • When changing the M counter, N counter, or loop filter settings, the I/O PLL may lose and regain lock. To maintain the appropriate phase relationship between the reference clock and output clocks, assert the areset signal to reset the PLL after reconfiguration is complete. Intel recommends always resetting the PLL after any reconfiguration operation to the M counter, N counter, or loop filter settings.
  • When changing the C counter settings, you may lose the expected phase relationship between the C counters. Assert the areset signal after reconfiguration is complete to restore the expected phase relationship. Reset is not required if the phase relationships are not important to your application.
  • Resetting the PLL does not modify the counter or loop filter settings. However, resetting the PLL undoes any dynamic phase shift operations that were performed. After the PLL is reset, the phase shift on the C counters is restored to the originally programmed settings.

Configuration Constraints

The I/O PLL configuration must obey the following constraints:

  • The phase frequency detector (PFD) and VCO each have a legal frequency range of operation.
  • The loop filter settings must be appropriate for the M counter value and user-selected bandwidth mode.

If any of these configuration constraints are violated, the I/O PLL may fail to lock or may exhibit poor jitter performance.

If you reconfigure the PLL using .mif streaming, the IOPLL IP core always produce legal PLL configurations in the auto-generated .mif file.

You must ensure that the PLL settings are legal if you apply the PLL reconfiguration write operations directly. The IOPLL IP core parameter editor provides several methods to identify the legal PLL configurations and to explore the combination of legal configurations.

Timing Closure

  • Reconfiguring a PLL's counter and loop filter settings changes both the output frequency and the clock uncertainty of that PLL. Dynamic phase shift only affects the output clock phase.
  • The Timing Analyzer in the Intel® Quartus® Prime software performs timing analysis for the initial PLL settings only. You must verify that your design closes timing after dynamic reconfiguration or dynamic phase shift.
  • Intel recommends compiling PLL designs with each intended configuration setting to determine the variation in the clock with PLL settings.

Other Design Considerations

  • I/O PLL reconfiguration interface supports a free running mgmt_clk signal. I/O PLL dynamic phase shift interface supports a free running scanclk signal. These interfaces eliminate the need to precisely control the start and stop of mgmt_clk and scanclk signals.
  • Reconfiguration commands are queued in the PLL Reconfig IP core, and removed after they are complete. Assert a high pulse on the mgmt_reset signal to reset the IP core to its initial state, clearing any queued commands.
  • Use caution when reconfiguring a PLL with a non-zero phase shift setting. Modifying the M counter or N counter settings does not change the relative phase shift (in percent), but alters the absolute phase shift (in picoseconds). Modifying the C counter settings does not change the absolute phase shift, but modifies the relative phase shift.
  • When writing to the PLL Reconfig IP core using a Nios® processor's Avalon® memory-mapped interface master, use the default Nios® word-addressing scheme. The Nios® processor produces an 11-bit address. The Platform Designer automatically converts this 11-bit address into the appropriate 9-bit address as required by the PLL Reconfig IP core.