AN 728: I/O PLL Reconfiguration and Dynamic Phase Shift for Intel® Arria® 10 and Intel Cyclone® 10 GX Devices

ID 683845
Date 8/08/2022
Document Table of Contents

Design Example 3: I/O PLL Dynamic Phase Shift

This design example uses the same device and pin assignments as in Design Example 1 and Design Example 2. This design example demonstrates the implementation of the I/O PLL dynamic phase shift in the IOPLL IP core.

The I/O PLL synthesizes two output clocks of 200 MHz with 0 ps phase shift on counter C0 output and counter C1 output at medium bandwidth. The input reference clock is 50 MHz.

The dynamic phase shift ports of the IOPLL IP core connect to a state machine to perform I/O PLL dynamic phase shift operation. A low pulse on the reset_SM input through the In-System Sources & Probes IP core triggers the I/O PLL dynamic phase shift operation. After I/O PLL dynamic phase shift operation is complete, counter C1 is phase shifted 208 ps for one positive phase shift step.

To run the test with the design example, perform these steps:

  1. Download and restore the an728-iopll-dynamic_phase_shift.qar file.
  2. If necessary, change the device and pin assignments (refclk, c0_out, c1_out, and locked pins) of the design example to match your hardware.
  3. Recompile the design example. Ensure that the design example does not contain any timing violation after recompilation.
  4. Open the AN.spf and program the device with test.sof.
  5. Assert a high pulse on reset_SM signal to start the I/O PLL dynamic phase shift operation.
Figure 6. Waveform Example for I/O PLL Dynamic Phase Shift Design Example