AN 728: I/O PLL Reconfiguration and Dynamic Phase Shift for Intel® Arria® 10 and Intel Cyclone® 10 GX Devices

ID 683845
Date 8/08/2022
Document Table of Contents

Write Operation for .mif Streaming Reconfiguration

The dynamic reconfiguration commands can also be stored in a .mif file for .mif streaming reconfiguration. To enable .mif streaming in the PLL Reconfig IP core, select the appropriate checkbox in the parameter editor and provide the path to the .mif file before generating your IP core.

To perform .mif streaming reconfiguration, follow these steps:

  1. Set the start .mif address (9'b000010000) for mgmt_address and the base address within the ROM for mgmt_writedata. To start the .mif streaming operation of I/O PLL reconfiguration, assert the mgmt_write signal for one mgmt_clk cycle.
  2. After the reconfiguration is complete, the mgmt_waitrequest signal is de-asserted.
You should not write to the start address (9'b0) in the .mif file.