AN 728: I/O PLL Reconfiguration and Dynamic Phase Shift for Intel® Arria® 10 and Intel Cyclone® 10 GX Devices

ID 683845
Date 8/08/2022
Document Table of Contents

I/O PLL Reconfiguration Read Operation

To perform a read operation for I/O PLL reconfiguration in the PLL Reconfig IP core, follow these steps:

  1. Set the address bus value for mgmt_address. To enable and start the read operation for I/O PLL reconfiguration, assert mgmt_read for one mgmt_clk cycle.
  2. After the read operation is complete, the mgmt_waitrequest signal is de-asserted. At the same time, read the data available from mgmt_readdata port.
With I/O PLL reconfiguration read operation, you can read the current I/O PLL settings. This operation is only supported for counter settings and bandwidth settings. Each read operation retrieves data from a single address. An I/O PLL reconfiguration read operation requires at least three mgmt_clk cycles of latency.