The following examples provide instructions for implementing functions using Verilog HDL. For more information on Verilog support, refer to Intel® Quartus® Prime Software Help.
For more examples of Verilog designs for Intel devices, refer to the recommended HDL coding styles chapter of the Intel Quartus Prime Software user guides. You can also access Verilog HDL examples from the language templates in the Intel Quartus Prime software.
Verilog Digital Signal Processing (DSP) Functions
- Verilog HDL Template for Inferring DSP Blocks in Stratix III and IV FPGAs
- Achieving Unity Gain in Block Floating-Point IFFT+FFT Pair
- Coefficient Reload for FIR Compiler
- FFT with 32K-Point Transform Length
- Signed Multiplier with Registered I/O
- Signed Multiplier-Adder
- Unsigned Multiplier
- Unsigned Multipier-Accumulator
How to Use Verilog HDL Examples
Intel provides Verilog HDL design examples as downloadable executable files or displayed as text in your web browser. Select the executable file link to download the file to your hard disk. To use Verilog HDL examples displayed as text in your Intel Quartus Prime software, copy and paste the text from your web browser into the Text Editor. Make sure that the file name of the Verilog HDL design file (.v) corresponds to the entity name in the example. For example, if the entity name is myram, save the file as myram.v.