Agilex™ 7 General-Purpose I/O User Guide: M-Series

ID 772138
Date 3/22/2024
Document Table of Contents

6.8.1. GPIO Intel® FPGA IP Synthesizable Quartus® Prime Design Example

The synthesizable design example is a compilation-ready Platform Designer system that you can include in an Quartus® Prime project.

Generating and Using the Design Example

To generate the synthesizable Quartus® Prime design example from the source files, run the following command in the design example directory:

quartus_sh -t make_qii_design.tcl

To specify an exact device to use, run the following command:

quartus_sh -t make_qii_design.tcl [device_name]

The TCL script creates a qii directory that contains the ed_synth.qpf project file. You can open and compile this project in the Quartus® Prime software.