Intel Agilex® 7 General-Purpose I/O User Guide: M-Series

ID 772138
Date 12/04/2023
Public
Document Table of Contents
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6.5.1. GPIO Intel® FPGA IP Data Paths

Figure 33.  High-Level View of Single-Ended GPIO-B


Table 53.   GPIO IP Data Path Modes
Data Path Register Mode
Bypass Simple Register DDIO
Input Data goes from the delay element to the core, bypassing all double data rate I/Os (DDIOs). The DDIO operates as a simple register. The Fitter chooses whether to pack the register in the I/O or implement the register in the core, depending on the area and timing trade-offs. The DDIO operates as a regular DDIO.
Output Data goes from the core straight to the delay element, bypassing all DDIOs.
Bidirectional The output buffer drives both an output pin and an input buffer. The DDIO operates as a simple register. The output buffer drives both an output pin and an input buffer. The DDIO operates as a regular DDIO. The output buffer drives both an output pin and an input buffer. The input buffer drives a set of three flip-flops.

If you use asynchronous clear and preset signals, all DDIOs share these same signals.