Intel Agilex® 7 General-Purpose I/O User Guide: M-Series

ID 772138
Date 12/04/2023
Public
Document Table of Contents
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2.4.1.4. Single-Ended I/O Termination Implementation Guide

To implement I/O termination in your design, you can assign the termination for your pin using the Intel® Quartus® Prime Assignment Editor or through the External Memory Interfaces Intel® FPGA IP and PHY Lite for Parallel Interfaces Intel® FPGA IP.