Intel Agilex® 7 General-Purpose I/O User Guide: M-Series

ID 772138
Date 12/04/2023
Public
Document Table of Contents
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2.5.3. VREF Sources and Input Standards Grouping

Consider these VREF sources guidelines.

M-Series devices support internal VREF sources. Each I/O lane in the bank also has its own internal VREF generator. You can configure VREF generator in the External Memory Interfaces Intel® FPGA IP and PHY Lite for Parallel Interfaces Intel® FPGA IP.

In each I/O lane, adhere to the input standards grouping to ensure all input pins in the I/O lane use the same internal VREF source. If the mix of input standards in an I/O lane does not adhere to these groupings, Intel® Quartus® Prime displays error messages during design compilation.

Note: Although the following table lists the groups based on VREF, the final rules depend on implementation. For example, the PHY Lite interface uses one I/O standard per I/O lane. If you use HSTL-12 and SSTL-12 with the PHY Lite for Parallel Interfaces IP, assign each I/O standard in a different I/O lane.
Table 21.  Input Standards Groups Per I/O Lane
Group Input Standards Mix within I/O Lane
Group 1
  • POD12
  • 1.2 V True Differential Signaling
  • 1.2 V LVCMOS
  • Differential POD12
Group 2
  • POD11
  • 1.1 V True Differential Signaling
  • 1.1 V LVCMOS
  • Differential POD11
Group 3
  • SSTL-12
  • HSTL-12
  • HSUL-12
  • 1.2 V True Differential Signaling
  • 1.2 V LVCMOS
  • Differential SSTL-12
  • Differential HSTL-12
  • Differential HSUL-12
Group 4
  • 1.1 V True Differential Signaling 7
  • LVSTL11
  • 1.1 V LVCMOS
  • Differential LVSTL11
Group 5
  • 1.05 V True Differential Signaling 7
  • LVSTL105
  • LVSTL700
  • 1.05 V LVCMOS
  • Differential LVSTL105
  • Differential LVSTL700
7 You can mix LVSTL I/O standard with True Differential Signaling I/O standard only if you use the True Differential Signaling input as a reference clock.