Intel Agilex® 7 General-Purpose I/O User Guide: M-Series

ID 772138
Date 12/04/2023
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7. Programmable I/O Features Description

Table 60.  I/O Features and Description
I/O Features Description
Programmable Output Slew Rate Control

Each I/O pin contains a slew rate control, allowing you to specify the slew rate on a pin-by-pin basis. The slew rate control affects both the rising and falling edges of the signal.

A faster slew rate provides high-speed transitions for high-performance systems while a slower slew rate reduces system noise and crosstalk but adds a nominal delay to the rising and falling edges.

Programmable IOE Delay

You can activate the programmable IOE delays to ensure zero hold time, minimize setup time, or increase the clock-to-output time. This feature helps read and write timing margins because it minimizes the uncertainties between signals on the bus.

Each pin can have a different input delay from the pin-to-input register or a delay from output register-to-output pin values. This is to ensure that the signals within a bus have the same delay going into or out of the device.

Programmable Pull-Up Resistor

Each I/O pin on supported banks provides an optional programmable pull-up resistor during user mode. The pull-up resistor weakly holds the I/O to the I/O bank power supply level.

Programmable Pull-Down Resistor

Each I/O pin on supported banks provides an optional programmable pull-down resistor during user mode. The pull-down resistor weakly holds the I/O to the ground level.

Programmable Pre-Emphasis

Pre-emphasis momentarily boosts the high-frequency component of the output signal during switching to increase the output slew rate. The amount of pre-emphasis required depends on the attenuation of the high-frequency component along the transmission line.

For more information, refer to Programmable Pre-Emphasis.

Programmable De-Emphasis

De-emphasis attenuates the I/O signal height when the symbol is longer than the specified duration. You can use de-emphasis to alter the signal amplitude to compensate for signal degradation over long transmission path.

For more information, refer to Programmable De-Emphasis.

Receiver Equalization Calibration

The FPGAs support two types of receiver equalization calibration:

  • Continuous Time Linear Equalization (CTLE)—all input buffers support CTLE except for the 1.05 V, 1.1 V, and 1.2 V LVCMOS I/O standards. You can turn on CTLE for all external memory interface implementation except DDR5 and LPDDR5.
  • Decision Feedback Equalization (DFE)—you can turn on DFE for DDR5 and LPDDR5 external memory interface implementations.

For more information, refer to:

Programmable Differential Output Voltage

The programmable VOD settings allow you to adjust the output eye-opening to optimize the trace length and power consumption. A higher VOD swing improves voltage margins at the receiver end, and a smaller VOD swing reduces power consumption.

For more information, refer to Programmable Differential Output Voltage.

Schmitt Trigger

The Schmitt Trigger allows input buffers to respond to slow input edge rates with a fast output edge rate. Most importantly, Schmitt Triggers provide hysteresis on the input buffer, preventing slow-rising noisy input signals from ringing or oscillating on the input signal driven into the logic array.

This feature provides system noise tolerance on the device inputs but adds a small, nominal input delay.

On-Die Termination Impedance The HPS and SDM input pins support on-die pull-up and pull-down termination. The on-die termination provides impedance matching and termination capabilities. You can enable this feature on input operations to minimize reflections and improve electrical margins.