Intel Agilex® 7 General-Purpose I/O User Guide: M-Series

ID 772138
Date 12/04/2023
Public
Document Table of Contents
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2.5.6. I/O Standards Implementation Based on VCCIO_PIO Voltages

The following guidelines apply to I/O standards based on the VCCIO_PIO voltages.

1.2 V, 1.1 V, or 1.05 V VCCIO_PIO

If you use a 1.2 V, 1.1 V, or 1.05 V VCCIO_PIO, you can implement single-ended non-voltage referenced and voltage-referenced I/O standards. The 1.2 V, 1.1 V, or 1.05 V buffer also supports differential voltage-referenced I/O and true differential input standards.

You can implement a mix of both voltage-referenced and non-voltage referenced I/O, and true differential input standards within the I/O bank if all the I/O standards support the VCCIO_PIO of the I/O bank.

1.3 V VCCIO_PIO

If you use a 1.3 V VCCIO_PIO voltage, you can implement both 1.3 V LVCMOS and True Differential Signaling I/O standards in the same I/O lane and sub-bank. The buffer can interface with upstream or downstream devices that are compatible with the M-Series FPGAs electrical specifications.

If you use True Differential Signaling input, analyze the electrical specification requirement to implement your true differential receiver.

Implement DC coupling if the signal swing and VICM voltage requirement are within the M-Series True Differential Signaling standard specification. Otherwise, implement AC coupling and external bias circuitry.