Intel Agilex® 7 General-Purpose I/O User Guide: M-Series

ID 772138
Date 12/04/2023
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2.5.14. GPIO-B Pins During Power Sequencing

M-Series devices do not support hot-socketing and require a specific power sequence. Design your power supply solution to properly control the complete power sequence.

Adhere to the these guidelines to prevent unnecessary current draw on the I/O pins located in the GPIO-B banks. These guidelines apply for unpowered, power up to power-on reset (POR), POR delay, POR delay to configuration, configuration, initialization, user mode, and power down device states.

  • The I/O pins in the GPIO-B banks can be tri-stated, driven to ground, or driven to the VCCIO_PIO level.
  • While the device is powering up or down:
    • The input signals of an I/O pin, at all times, must not exceed the I/O buffer power supply rail of the bank where the I/O pin resides.
    • If you use a pin in a GPIO-B bank with 1.3 V VCCIO_PIO, the pin voltage must not exceed the VCCIO_PIO rail or 1.2 V, whichever is lower.
  • While the device is powering up or powering down, the GPIO-B pins can tolerate a maximum of 10 mA per pin and a total of 100 mA per GPIO-B bank.
  • While the device is not turned on, tri-state the I/O pin and do not drive the pin with any external voltage.
  • After the device fully powers up, the voltage levels for the GPIO-B pins must not exceed the DC input voltage (VI) value.
Table 22.  Guideline Examples
Condition Guideline
The VCCIO_PIO pin ramps up and at period X, the VCCIO_PIO voltage is 1.1 V. At period X, keep the signals driven by the device connected to the GPIO-B I/O pin at a voltage of 1.1 V or lower.
The 1.3 V VCCIO_PIO pin ramps up and the voltage continues to rise pass the 1.2 V level. Keep the GPIO-B pin voltage at 1.2 V or lower until the device fully powers up.