Intel Agilex® 7 General-Purpose I/O User Guide: M-Series

ID 772138
Date 12/04/2023
Public
Document Table of Contents
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3.5.2. Net Length Reports

The net length information consists of the package trace delay from the die pad to the package pin. Each pin in an FPGA package has its own net length information. This information is important for you to perform board trace compensation to optimize the channel-to-channel skew on your board design.