Intel Agilex® 7 General-Purpose I/O User Guide: M-Series

ID 772138
Date 12/04/2023
Public
Document Table of Contents
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6.7.3.2. DDIO Input Register

You can properly constrain the system by using a virtual clock to model the off-chip transmitter to the FPGA.
Figure 43. DDIO Input Register


Table 57.  DDIO Input Register .sdc Command Examples
Command Command Example Description
create_clock

create_clock -name virtual_clock -period "200 MHz"

create_clock -name ddio_in_clk -period "200 MHz" ddio_in_clk

Create clock setting for the virtual clock and the DDIO clock.
set_input_delay

set_input_delay -clock virtual_clock 0.25 ddio_in_data

set_input_delay -add_delay -clock_fall -clock virtual_clock 0.25 ddio_in_data

Instruct the Timing Analyzer to analyze the positive clock edge and the negative clock edge of the transfer. Note the -add_delay in the second set_input_delay command.
set_false_path

set_false_path -fall_from virtual_clock -rise_to ddio_in_clk

set_false_path -rise_from virtual_clock -fall_to ddio_in_clk

Instruct the Timing Analyzer to ignore the positive clock edge to the negative edge triggered register, and the negative clock edge to the positive edge triggered register.