Intel Agilex® 7 General-Purpose I/O User Guide: M-Series

ID 772138
Date 12/04/2023
Public
Document Table of Contents
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2.5.2. Placement Restrictions for True Differential and Single-Ended I/O Standards in the Same or Adjacent GPIO-B Bank

If you use true differential I/O standards and single-ended I/O standards in the same or adjacent GPIO-B banks, adhere to the following placement guidelines. These restrictions do not apply to differential reference clock that feeds directly into the PLL reference clock ports.
  • Do not place true differential and toggling single-ended I/O standards in the combinations of locations listed in the following tables.
  • From version 24.1, the Intel® Quartus® Prime software issues the following errors:
    • Compilation error—violation of the same bank placement restriction.
    • Critical warning—assignment of true differential I/O standards to pin pairs with the following pin index numbers: 0 and 1, 6 and 7, 88 and 89, and 94 and 95.
Table 19.  Restricted Pin Placement Combinations for True Differential and Single-Ended I/O Standards in the Same GPIO-B Bank

This table lists the combinations of pins and I/O standards not allowed in the same GPIO-B bank. Examples:

  • If you place a true differential I/O standard in pin pair 10 and 11, do not place single-ended I/O standards in pins 9 or 18.
  • If you place a single-ended I/O standard in pin 57 or 66, do not place a true differential I/O standard in pin pair 58 and 59.
Combinations Not Allowed (Pin Index Number) Combinations Not Allowed (Pin Index Number) Combinations Not Allowed (Pin Index Number) Combinations Not Allowed (Pin Index Number)
True Differential Pin Pair Single-Ended Pin True Differential Pin Pair Single-Ended Pin True Differential Pin Pair Single-Ended Pin True Differential Pin Pair Single-Ended Pin
0 and 1 2 24 and 25 17, 26 48 and 49 41, 50 72 and 73 65, 74
2 and 3 1, 4 26 and 27 25, 28 50 and 51 49, 52 74 and 75 73, 76
4 and 5 3, 12 28 and 29 27, 36 52 and 53 51, 60 76 and 77 75, 84
6 and 7 8 30 and 31 23, 32 54 and 55 47, 56 78 and 79 71, 80
8 and 9 7, 10 32 and 33 31, 34 56 and 57 55, 58 80 and 81 79. 82
10 and 11 9, 18 34 and 35 33, 42 58 and 59 57, 66 82 and 83 81, 90
12 and 13 5, 14 36 and 37 29, 38 60 and 61 53, 62 84 and 85 77, 86
14 and 15 13, 16 38 and 39 37, 40 62 and 63 61, 64 86 and 87 85, 88
16 and 17 15, 24 40 and 41 39, 48 64 and 65 63, 72 88 and 89 87
18 and 19 11, 20 42 and 43 35, 44 66 and 67 59, 68 90 and 91 83, 92
20 and 21 19, 22 44 and 45 43, 46 68 and 69 67, 70 92 and 93 91, 94
22 and 23 21, 30 46 and 47 45, 54 70 and 71 69, 78 94 and 95 93
Table 20.  Restricted Pin Placement Combinations for True Differential and Single-Ended I/O Standards in Adjacent GPIO-B Banks

This table lists the combinations of pins and I/O standards not allowed in adjacent GPIO-B banks. Examples:

  • If you place a true differential I/O standard in pin pair 6 and 7 of bank 3B, do not place single-ended I/O standards in pin 95 of bank 3A.
  • If you place a single-ended I/O standard in pin 0 of bank 2C, do not place a true differential I/O standard in pin pair 88 and 89 of bank 2D.
Combinations Not Allowed (Pin Index Number) Combinations Not Allowed (Pin Index Number)
True Differential Single-Ended True Differential Single-Ended
Bank Pin Pair Bank Pin Bank Pin Pair Bank Pin
3A 88 and 89 3B 0 2A 88 and 89 2B 89
94 and 95 6 94 and 95 95
3B 0 and 1 3A 89 2B 0 and 1 2C 89
6 and 7 95 6 and 7 95
88 and 89 3C 89 88 and 89 2A 89
94 and 95 95 94 and 95 95
3C 0 and 1 3D 89 2C 0 and 1 2D 89
6 and 7 95 6 and 7 95
88 and 89 3B 89 88 and 89 2B 0
94 and 95 95 94 and 95 6
3D 88 and 89 3C 0 2D 88 and 89 2C 0
94 and 95 6 94 and 95 6

Refer to the related information for the figure showing the locations of the GPIO-B banks.