Intel Agilex® 7 General-Purpose I/O User Guide: M-Series

ID 772138
Date 12/04/2023
Public
Document Table of Contents

3.3.1. Configuring Open Drain Feature for the HPS I/O

You can turn on the open drain feature for the HPS I/Os through the Hard Processor System Intel Agilex 7 FPGA IP in the Intel® Quartus® Prime Platform Designer.
Figure 24.  Hard Processor System Intel Agilex 7 FPGA IP Parameter Editor


  1. From the Intel® Quartus® Prime menu, select Tools > Platform Designer
  2. Specify the Quartus project and Platform Designer system, then click Open.
  3. In Platform Designer, open the Hard Processor System Intel Agilex 7 FPGA IP parameter editor.
  4. Navigate to the Pin Mux and Peripherals > Pin Mux GUI > Advanced > Advanced IP Placement tab.
  5. If you make any changes, click Apply Selections, then click OK.
  6. Scroll down to the HPS IO Open Drain Select section.
  7. Turn on the HPS IONN Open Drain Enable that you want.
Figure 25. HPS IO Open Drain Select Section