Intel Agilex® 7 General-Purpose I/O User Guide: M-Series

ID 772138
Date 12/04/2023
Public
Document Table of Contents
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2.1.1. GPIO-B Bank Structure

Figure 2.  GPIO-B Bank Structure (Die Top View)This figure shows the GPIO-B bank structure of the M-Series FPGA. The figure shows the view of the die as shown in the Intel® Quartus® Prime Chip Planner. In the Pin Planner, this corresponds to the "Bottom View". Different device packages have different number of GPIO-B banks. Refer to the device pin-out files for available GPIO-B banks and the locations of the SDM and HPS shared I/O banks for each device package.