Intel Agilex® 7 General-Purpose I/O User Guide: M-Series

ID 772138
Date 12/04/2023
Public
Document Table of Contents

6.5.2. Register Packing

The GPIO IP allows you to pack registers into the periphery to save area and resource utilization.

You can configure the DDIO on the input and output path as a flip flop by adding .qsf assignments.

Table 54.  Register Packing .qsf Assignments
Path .qsf Assignment
Input register packing set_instance_assignment -name FAST_INPUT_REGISTER ON -to <path to register>
Output register packing set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to <path to register>
Output enable register packing set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to <path to register>
Note: The .qsf assignments do not guarantee register packing. However, these assignments enable the Fitter to find a legal placement. Otherwise, the Fitter keeps the flip flop in the core.