Agilex™ 7 General-Purpose I/O User Guide: M-Series

ID 772138
Date 3/22/2024
Public
Document Table of Contents

5. Intel Agilex® 7 M-Series I/O Troubleshooting Guidelines

These debug guidelines are initial debug actions and do not necessarily resolve the failures in your designs.
Table 42.  GPIO Debug GuidelinesThis table lists the failure symptoms and the associated debug actions that you can take to identify the failure areas when you are designing GPIO systems with M-Series devices.
Failure Symptoms Recommended Debug Actions

1.2 V LVCMOS output at the entire bank does not reach 1.2 V.

  • Check the power-up and power-down sequences of each voltage rail with respect to time.
  • Compare the power sequences as per recommendation in the Intel Agilex® 7 Power Management User Guide: M-Series .
  • Verify the VCCIO_PIO voltage signal is 1.2 V.

Intel® Quartus® Prime software shows an error message to indicate incorrect I/O settings for VCCIO during design compilation.

Error message example: Illegal constraint of I/O bank to the location <I/O bank>

Select the I/O pins specified in the error message and check the I/O settings for the pins.

Intel® Quartus® Prime software shows illegal I/O error message during design compilation.

Error message example: Programmable VOD option is set to 1 for pin <pin_name>, but setting is not supported by <I/O standard>

Select the I/O pins specified in the error message and set the pins to the correct I/O function. Refer to the device pin-outs file for more information about the pin functions.