Multi Channel DMA Intel® FPGA IP for PCI Express User Guide

ID 683821
Date 8/19/2022

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Document Table of Contents

6.1.1. Top-Level Settings

Figure 19. Multi Channel DMA IP for PCI Express Parameter Editor
Table 65.  Top-Level Settings



Default Value


Hard IP mode

Gen4x16, Interface – 512 bit

Gen3x16, Interface – 512 bit

Gen4x8, Interface – 256 bit

Gen3x8, Interface – 256 bit

Gen4x16, Interface – 512 bit

Selects the following elements:

  • The lane data rate. Gen3 and Gen4 are supported
  • This is selected by PLD Clock Frequency parameter.
  • The width of the data interface between the hard IP Transaction Layer and the Application Layer implemented in the FPGA fabric.
Number of PCIe 1 1

Display total number of MCDMA IP cores.

Note: In the current release, MCDMA IP in x8 mode supports single MCDMA IP core (PCIe0) regardless of the Hard IP mode.
Port Mode

Native Endpoint

Root Port

Native Endpoint

Specifies the port type.

Enable Ptile Debug Toolkit (P-Tile)

Enable Debug Toolkit (F-Tile)

On / Off


Enable the Debug Toolkit for JTAG-based System Console debug access.

Enable PHY Reconfiguration

On / Off


When on, creates an Avalon-MM slave interface that software can drive to update Transceiver reconfiguration registers

Enable the transceiver PMA registers access thru a dedicated an Avalon-MM slave interface.

Note: In F-Tile, this option has renamed as Enable PMA registers access

PLD Clock Frequency

500 MHz

450 MHz

400 MHz

350 MHz

350 MHz (for Gen4 modes)

250 MHz (for Gen3 modes)

Select the frequency of the Application clock. The options available vary depending on the setting of the Hard IP Mode parameter.

For Gen4 modes, the available clock frequencies are 500 MHz / 450 MHz / 400 MHz / 350 MHz (for Intel Agilex) and 400 MHz / 350 MHz (for Intel Stratix 10 DX).

For Gen3 modes, the available clock frequency is 250 MHz (for Intel Agilex and Intel Stratix 10 DX).

Enable SRIS Mode

On / Off


Enable the Separate Reference Clock with Independent Spread Spectrum Clocking (SRIS) feature.

When you enable this option, the Slot clock configuration option under the PCIe Settings → PCIe PCI Express/PCI Capabilities → PCIe Link tab will be automatically disabled.

P-Tile Sim Mode

On / Off


Enabling this parameter reduces the simulation time of Hot Reset tests by 5 ms.

Default: False

Note: Do not enable this option if you need to run synthesis.
Note: This option is not available for F-Tile.
Enable CVP (Intel VSEC) On / Off Off

Enable support for CVP flow for single tile only

Refer to Intel Agilex Device Configuration via Protocol (CvP) Implementation User Guide for more information