Multi Channel DMA Intel® FPGA IP for PCI Express User Guide

ID 683821
Date 8/19/2022

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Document Table of Contents

5.1.1. System Settings

Figure 15. Multi Channel DMA IP for PCI Express Parameter Editor
Table 53.  System Settings




Hard IP mode

Gen3x16, Interface - 512-bit, 250 MHz

Gen3x8, Interface - 256 bit, 250 MHz

Selects the following elements:

  • The lane data rate. Gen3 is supported
  • The Application Layer interface frequency

The width of the data interface between the hard IP Transaction Layer and the Application Layer implemented in the FPGA fabric.

Port type

Native Endpoint

Root Port

Specifies the port type.

Enable multiple physical functions On / Off

This parameter is not user configurable.

This is automatically turned on when you select Total physical functions (PFs) greater than 1 in Multifunction and SR-IOV System Settings tab.