Multi Channel DMA Intel® FPGA IP for PCI Express User Guide

ID 683821
Date 8/19/2022
Public

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3.2. Bursting Avalon-MM Master (BAM)

The BAM bypasses the Multi Channel DMA IP for PCI Express & provides a way for a Host to perform bursting PIO read/writes to the user logic. The BAM converts memory read and write TLPs initiated by the remote link partner and received over the PCIe link into Avalon-MM burst read and write transactions, and sends back CplD TLPs for read requests it receives. Since the BAM user interface is Avalon-MM, the completions are always expected in order from user logic/Qsys fabric. The BAM supports bursts of up to 512 bytes and up to 32 outstanding read request.

BAM Address Mapping

You can select to map any BAR register other than the BAR0 of the physical function to BAM side for the user application. The BAM interface address mapping is as follows:
BAM address = {vf_active, pf, vf, bar_num, bam_addr} 
  1. vf_active: This indicates that SRIOV is enabled
  2. pf [PF_NUM-1:0]: Physical function number decoded from the PCIe header received from the HIP; PF_NUM which is ($clog2(Number of PFs)) is the RTL design parameter selected by the user such that Multi Channel DMA only allocates required number of the bits on Avalon-MM side to limit the number of the wires on the user interface. Example: If the number of PFs selected by user is 4, the PF_NUM is 2.
  3. vf [VF_NUM-1:0]: Virtual function number decoded from the PCIe header received from the HIP; VF_NUM which is ($clog2(Number of VFs)) is the RTL design parameter selected by the user such that Multi Channel DMA only allocates required number of the bits on Avalon-MM side to limit the number of the wires on the user interface. Example: If the total number of VFs across all PFs selected by user is 32, the VF_NUM is 5.
  4. bar_num [2:0]: This denotes the BAR number where the Avalon-ST transaction was received.
  5. bam_addr [ADDR_SIZE-1:0]: Lower address based on the maximum aperture size amongst all the BARs. Example: If BAR3 is selected as 16 MB and BAR2 is 4 GB, the ADDR_SIZE = 32 corresponding to BAR2.

Example: If the transaction was received for BAR3 (max aperture of 4GB) of PF2/VF1 where only 3 PFs have been enabled by the user, 25 VFs have been enabled by the user, the BAM address is {1'b1, 2'b10, 5'b00001, 3'b011, bam_addr[31:0]}.

Note: For the Root Port: In the Root Port mode, the AVMM address output from BAM is the same as the one received on the Hard IP AVST.

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