Multi Channel DMA Intel® FPGA IP for PCI Express User Guide

ID 683821
Date 8/19/2022

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4.4.7. User Functional Level Reset (FLR) Interface

When the DMA engine receives Functional Level Resets from the PCle Hard IP module, the reset requests are propagated to the downstream logic via this interface. In addition to performing resets to its internal logic, the FLR interface waits for an acknowledgment from user logic for the reset request before it issues an acknowledgement to the PCle Hard IP.

Table 40.  User FLR Interface

Interface Clock Domain for H-Tile: coreclkout_hip

Interface Clock Domain for P-Tile and F-Tile: app_clk

Signal Name I/O Description


Indicates user logic to begin flr for the specifid channel in usr_flr_rcvd_chan_num_o. asserted until usr_flr_completed_i input is sampled 1’b1.



Indicates Channel number for which flr has to be initiated by user logic.



One-cycle pulse from the application indicates completion of flr activity for channel in usr_flr_rcvd_chan_num_o