Multi Channel DMA Intel® FPGA IP for PCI Express User Guide

ID 683821
Date 8/19/2022
Public

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3.6. Config TL Interface

The Config TL interface extracts the required information stored in the PCIe Hard IP config space in order for the DMA to operate properly. Some of the example includes MPS, MRRS, and Bus Master Enable.

The configuration register extraction only occurs periodically, so the assumption is made that these are fairly static signals and there are significant delays after the config space is updated by software.

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