Multi Channel DMA Intel® FPGA IP for PCI Express User Guide

ID 683821
Date 8/19/2022
Public

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10.1.4.1. Main View

The main view tab lists a summary of the transmitter and receiver settings per channel for the given instance of the PCIe IP.

The following table shows the channel mapping when using bifurcated ports.

Table 160.  Channel Mapping for Bifurcated Ports
Toolkit Channel X16 Mode X8 Mode
Lane 0 Lane 0 Lane 0
Lane 1 Lane 1 Lane 1
Lane 2 Lane 2 Lane 2
Lane 3 Lane 3 Lane 3
Lane 4 Lane 4 Lane 4
Lane 5 Lane 5 Lane 5
Lane 6 Lane 6 Lane 6
Lane 7 Lane 7 Lane 7

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