Multi Channel DMA Intel® FPGA IP for PCI Express User Guide

ID 683821
Date 8/19/2022
Public

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3.1.5. Avalon-MM Write (H2D) and Read (D2H) Master

Avalon-MM Interface is used to transfer data between the host and device through the memory-mapped interface. You can enable the Memory-Mapped interface by selecting AVMM Interface type in the IP Parameter Editor. The Multi Channel DMA IP for PCI Express supports 1 write master port and 1 read master port.

Avalon-MM Write Master

The Avalon-MM Write Master is used to write H2D DMA data to the Avalon-MM slave in the user logic through the memory-mapped interface. The Write Master can issue AVMM write commands for up to 8 bursts (burst count = 8). The waitrequestAllowance of this port is enabled and set to 16, allowing the master to transfer up to 16 additional write command cycles after the waitrequest signal has been asserted.

Figure 5. Avalon-MM Write with waitrequestAllowance 16

Avalon-MM Read Master

The Avalon-MM Read Master is used to read D2H DMA data from the Avalon-MM slave in the user logic through the memory-mapped interface. The Read Master can issue AVMM read commands for up to 8 bursts (burst count = 8).

Figure 6. Avalon-MM Read Master Timing Diagram

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